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National Semiconductor Electronic Components Datasheet

74F163ASC Datasheet

Synchronous Presettable Binary Counter

No Preview Available !

74F163ASC pdf
November 1994
54F 74F161A  54F 74F163A
Synchronous Presettable Binary Counter
General Description
The ’F161A and ’F163A are high-speed synchronous modu-
lo-16 binary counters They are synchronously presettable
for application in programmable dividers and have two types
of Count Enable inputs plus a Terminal Count output for
versatility in forming synchronous multi-stage counters The
’F161A has an asynchronous Master-Reset input that over-
rides all other inputs and forces the outputs LOW The
’F163A has a Synchronous Reset input that overrides
counting and parallel loading and allows the outputs to be
simultaneously reset on the rising edge of the clock The
’F161A and ’F163A are high-speed versions of the ’F161
and ’F163
Features
Y Synchronous counting and loading
Y High-speed synchronous expansion
Y Typical count frequency of 120 MHz
Y Guaranteed 4000V minimum ESD protection
Commercial
Military
Package
Number
Package Description
74F161APC
N16E
16-Lead (0 300 Wide) Molded Dual-In-Line
54F161ADM (Note 2) J16A
16-Lead Ceramic Dual-In-Line
74F161ASC (Note 1)
M16A
16-Lead (0 150 Wide) Molded Small Outline JEDEC
74F161ASJ (Note 1)
M16D
16-Lead (0 300 Wide) Molded Small Outline EIAJ
54F161AFM (Note 2) W16A
16-Lead Cerpack
54F161ALM (Note 2) E20A
20-Lead Ceramic Leadless Chip Carrier Type C
74F163APC
N16E
16-Lead (0 300 Wide) Molded Dual-In-Line
54F163ADM (Note 2) J16A
16-Lead Ceramic Dual-In-Line
74F163ASC (Note 1)
M16A
16-Lead (0 150 Wide) Molded Small Outline JEDEC
74F163ASJ (Note 1)
M16D
16-Lead (0 300 Wide) Molded Small Outline EIAJ
54F163AFM (Note 2) W16A
16-Lead Cerpack
54F163ALM (Note 2) E20A
20-Lead Ceramic Leadless Chip Carrier Type C
Note 1 Devices also available in 13 reel Use suffix e SCX and SJX
Note 2 Military grade device with environmental and burn-in processing Use suffix e DMQB FMQB and LMQB
Connection Diagrams
Pin Assignment
for DIP SOIC and Flatpak
’F161A
Pin Assignment
for LCC
’F161A
Pin Assignment
for DIP SOIC and Flatpak
’F163A
Pin Assignment
for LCC
’F163A
TL F 9486–1
TL F 9486 – 2
TRI-STATE is a registered trademark of National Semiconductor Corporation
C1995 National Semiconductor Corporation TL F 9486
TL F 9486 – 7
TL F 9486 – 8
RRD-B30M75 Printed in U S A



National Semiconductor Electronic Components Datasheet

74F163ASC Datasheet

Synchronous Presettable Binary Counter

No Preview Available !

74F163ASC pdf
Logic Symbols
’F161A
IEEE IEC
’F161A
TL F 9486–3
’F163A
IEEE IEC
’F163A
TL F 9486 – 9
Unit Loading Fan Out
TL F 9486–6
Pin Names
CEP
CET
CP
MR (’F161A)
SR (’F163A)
P0 – P3
PE
Q0 – Q3
TC
Description
Count Enable Parallel Input
Count Enable Trickle Input
Clock Pulse Input (Active Rising Edge)
Asynchronous Master Reset Input (Active LOW)
Synchronous Reset Input (Active LOW)
Parallel Data Inputs
Parallel Enable Input (Active LOW)
Flip-Flop Outputs
Terminal Count Output
TL F 9486 – 10
54F 74F
UL
HIGH LOW
10 10
10 20
10 10
10 10
10 20
10 10
10 20
50 33 3
50 33 3
Input IIH IIL
Output IOH IOL
20 mA b0 6 mA
20 mA b1 2 mA
20 mA b0 6 mA
20 mA b0 6 mA
20 mA b1 2 mA
20 mA b0 6 mA
20 mA b1 2 mA
b1 mA 20 mA
b1 mA 20 mA
2



National Semiconductor Electronic Components Datasheet

74F163ASC Datasheet

Synchronous Presettable Binary Counter

No Preview Available !

74F163ASC pdf
Functional Description
The ’F161A and ’F163A count in modulo-16 binary se-
quence From state 15 (HHHH) they increment to state 0
(LLLL) The clock inputs of all flip-flops are driven in parallel
through a clock buffer Thus all changes of the Q outputs
(except due to Master Reset of the ’F161A) occur as a re-
sult of and synchronous with the LOW-to-HIGH transition
of the CP input signal The circuits have four fundamental
modes of operation in order of precedence asynchronous
reset (’F161A) synchronous reset (’F163A) parallel load
count-up and hold Five control inputs Master Reset (MR
’F161A) Synchronous Reset (SR ’F163A) Parallel Enable
(PE) Count Enable Parallel (CEP) and Count Enable Trickle
(CET) determine the mode of operation as shown in the
Mode Select Table A LOW signal on MR overrides all other
inputs and asynchronously forces all outputs LOW A LOW
signal on SR overrides counting and parallel loading and
allows all outputs to go LOW on the next rising edge of CP
A LOW signal on PE overrides counting and allows informa-
tion on the Parallel Data (Pn) inputs to be loaded into the
Mode Select Table
SR PE CET
LXX
HL X
HHH
HH L
HH X
For ’F163A only
H e HIGH Voltage Level
L e LOW Voltage Level
X e Immaterial
CEP
X
X
H
X
L
Action on the Rising
Clock Edge (L)
Reset (Clear)
xLoad (Pn Qn)
Count (Increment)
No Change (Hold)
No Change (Hold)
flip-flops on the next rising edge of CP With PE and MR
(’F161A) or SR (’F163A) HIGH CEP and CET permit count-
ing when both are HIGH Conversely a LOW signal on ei-
ther CEP or CET inhibits counting
The ’F161A and ’F163A use D-type edge triggered flip-flops
and changing the SR PE CEP and CET inputs when the CP
is in either state does not cause errors provided that the
recommended setup and hold times with respect to the ris-
ing edge of CP are observed
The Terminal Count (TC) output is HIGH when CET is HIGH
and the counter is in state 15 To implement synchronous
multi-stage counters the TC outputs can be used with the
CEP and CET inputs in two different ways Please refer to
the ’F568 data sheet The TC output is subject to decoding
spikes due to internal race conditions and is therefore not
recommended for use as a clock or asynchronous reset for
flip-flops counters or registers
Logic Equations Count Enable e CEP  CET  PE
TC e Q0  Q1  Q2  Q3  CET
State Diagram
TL F 9486 – 5
3




Part Number 74F163ASC
Description Synchronous Presettable Binary Counter
Maker National Semiconductor
Total Page 10 Pages
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