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National Semiconductor Electronic Components Datasheet

74F138PC Datasheet

1-of-8 Decoder/Demultiplexer

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74F138PC pdf
November 1994
54F 74F138
1-of-8 Decoder Demultiplexer
General Description
The ’F138 is a high-speed 1-of-8 decoder demultiplexer
This device is ideally suited for high-speed bipolar memory
chip select address decoding The multiple input enables
allow parallel expansion to a 1-of-24 decoder using just
three ’F138 devices or a 1-of-32 decoder using four ’F138
devices and one inverter
Features
Y Demultiplexing capability
Y Multiple input enable for easy expansion
Y Active LOW mutually exclusive outputs
Y Guaranteed 4000V minimum ESD protection
Commercial
74F138PC
74F138SC (Note 1)
74F138SJ (Note 1)
Military
54F138DM (Note 2)
54F138FM (Note 2)
54F138LM (Note 2)
Package
Number
N16E
J16A
M16A
M16D
W16A
E20A
Package Description
16-Lead (0 300 Wide) Molded Dual-In-Line
16-Lead Ceramic Dual-In-Line
16-Lead (0 150 Wide) Molded Small Outline JEDEC
16-Lead (0 300 Wide) Molded Small Outline EIAJ
16-Lead Cerpack
20-Lead Ceramic Leadless Chip Carrier Type C
Note 1 Devices also available in 13 reel Use suffix e SCX and SJX
Note 2 Military grade device with environmental and burn-in processing Use suffix e DMQB FMQB and LMQB
Logic Symbols
Connection Diagrams
Pin Assignment for DIP
SOIC and Flatpak
Pin Assignment
for LCC
TL F 9478–3
IEEE IEC
TL F 9478 – 1
TL F 9478 – 2
TL F 9478–6
TRI-STATE is a registered trademark of National Semiconductor Corporation
C1995 National Semiconductor Corporation TL F 9478
RRD-B30M75 Printed in U S A



National Semiconductor Electronic Components Datasheet

74F138PC Datasheet

1-of-8 Decoder/Demultiplexer

No Preview Available !

74F138PC pdf
Unit Loading Fan Out
Pin Names
Description
A0 – A2
E1 E2
E3
O0 – O7
Address Inputs
Enable Inputs (Active LOW)
Enable Input (Active HIGH)
Outputs (Active LOW)
54F 74F
UL
HIGH LOW
10 10
10 10
10 10
50 33 3
Input IIH IIL
Output IOH IOL
20 mA b0 6 mA
20 mA b0 6 mA
20 mA b0 6 mA
b1 mA 20 mA
Functional Description
The ’F138 high-speed 1-of-8 decoder demultiplexer ac-
cepts three binary weighted inputs (A0 A1 A2) and when
enabled provides eight mutually exclusive active LOW out-
puts (O0 – O7) The ’F138 features three Enable inputs two
active LOW (E1 E2) and one active HIGH (E3) All outputs
will be HIGH unless E1 and E2 are LOW and E3 is HIGH
This multiple enable function allows easy parallel expansion
of the device to a 1-of-32 (5 lines to 32 lines) decoder with
just four ’F138 devices and one inverter (See Figure 1 ) The
’F138 can be used as an 8-output demultiplexer by using
one of the active LOW Enable inputs as the data input and
the other Enable inputs as strobes The Enable inputs which
are not used must be permanently tied to their appropriate
active HIGH or active LOW state
Truth Table
Inputs
E1 E2 E3 A0 A1 A2 O0 O1 O2
HXXX X XHH H
XHXX X XHH H
XXLXXXHH H
LLHL L L L H H
L LHH L L H L H
LLHLHLHH L
L LHHH L HH H
LLHL LHHH H
L LHH L HHH H
LLHLHHHH H
L LHHHHHH H
H e HIGH Voltage Level
L e LOW Voltage Level
X e Immaterial
Outputs
O3 O4 O5 O6 O7
HHHHH
HHHHH
HHHHH
HHHHH
HHHHH
HHHHH
L HHHH
H L HHH
HH L HH
HHH L H
HHHH L
2



National Semiconductor Electronic Components Datasheet

74F138PC Datasheet

1-of-8 Decoder/Demultiplexer

No Preview Available !

74F138PC pdf
Logic Diagram
TL F 9478 – 4
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays
3




Part Number 74F138PC
Description 1-of-8 Decoder/Demultiplexer
Maker National Semiconductor
Total Page 10 Pages
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