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National Semiconductor Electronic Components Datasheet

74C2525 Datasheet

1-to-8 Minimum Skew Clock Driver

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74C2525 pdf
September 1995
CGS74C2525  CGS74CT2525
CGS74C2526  CGS74CT2526
1-to-8 Minimum Skew Clock Driver
The CGS ’C CT2525 is a minimum skew clock driver with
one input driving eight outputs specifically designed for sig-
nal generation and clock distribution applications The ’2525
is designed to distribute a single clock to eight separate
receivers with low skew across all outputs during both the
tPLH and tPHL transitions The ’2526 is similar to the ’2525
but contains a multiplexed clock input to allow for systems
with dual clock speeds or systems where a separate test
clock has been implemented
Features
Y These CGS devices implement National’s FACTTM
family
Y Ideal for signal generation and clock distribution
Y Guaranteed pin to pin and part to part skew
Y Multiplexed clock input (’2526)
Y Guaranteed 2 kV minimum ESD protection
Y Symmetric output current drive of 24 mA for IOL IOH
Y ’CT has TTL-compatible inputs
Y These products are identical to 74AC ACT2525 and
2526
Y Available as Mil Aero versions
54AC ACT2525
54AC ACT2526
Logic Symbols
’2525
Connection Diagrams
Pin Assignment
for DIP and SOIC
’2525
’2526
TL F 10684 – 1
TL F 10684 – 2
’2526
TL F 10684 – 3
TRI-STATE is a registered trademark of National Semiconductor Corporation
FACTTM is a trademark of National Semiconductor Corporation
C1996 National Semiconductor Corporation TL F 10684
RRD-B30M106 Printed in U S A
TL F 10684 – 4
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National Semiconductor Electronic Components Datasheet

74C2525 Datasheet

1-to-8 Minimum Skew Clock Driver

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74C2525 pdf
Functional Description
On the multiplexed clock device the SEL pin is used to
determine which CLKn input will have an active effect on
the outputs of the circuit When SEL e 1 the CLK1 input is
selected and when SEL e 0 the CLK0 input is selected
The non-selected CLKn input will not have any effect on the
logical output level of the circuit The output pins act as a
single entity and will follow the state of the CLK or
CLK1 CLK0 pins when either the multiplexed (’2526) or the
straight (’2525) clock distribution chip is selected
Pin Description
Pin Names
Description
CLK
CLK0 CLK1
O0 – O7
SEL
Clock Input (’2525)
Clock Inputs (’2526)
Outputs
Clock Select (’2526)
’2525
Truth Tables
’2525
Inputs
Outputs
CLK
L
H
O0 – O7
L
H
’2526
Inputs
CLK0 CLK1 SEL
L XL
H XL
X LH
X HH
L e Low Voltage Level
H e High Voltage Level
X e Immaterial
Outputs
O0 – O7
L
H
L
H
’2526
TL F 10684–7
TL F 10684 – 8
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2



National Semiconductor Electronic Components Datasheet

74C2525 Datasheet

1-to-8 Minimum Skew Clock Driver

No Preview Available !

74C2525 pdf
Absolute Maximum Ratings (Note 1)
If Military Aerospace specified devices are required
please contact the National Semiconductor Sales
Office Distributors for availability and specifications
Supply Voltage (VCC)
DC Input Diode Current (IIK)
VI e b0 5V
VI e VCC a0 5V
DC Input Voltage (VI)
DC Output Diode Current (IOK)
VO e 0 5V
VO e VCC a0 5V
DC Output Voltage (VO)
DC Output Source
or Sink Current (IO)
DC VCC or Ground Current
per Output Pin (ICC or IGND)
Storage Temperature (TSTG)
Junction Temperature (iJA)
Plastic (N) 14-Lead
Plastic (M) 14-Lead
Plastic (N) 16-Lead
Plastic (M) 16-Lead
b0 5V to a7 0V
b20 mA
a0 2 mA
b0 5V to (VCC a0 5V)
b20 mA
a20 mA
b0 5V to (VCC a0 5V)
g50 mA
g50 MA
b65 C to a150 C
102 C W
128 C W
97 C W
124 C W
Recommended Operating
Conditions
Supply Voltage (VCC)
‘C’
‘CT’
2 0V to 6 0V
4 5V to 5 5V
Input Voltage (VI)
Output Voltage (VO)
Operating Temperature (TA)
CGS74C CT
54AC ACT
0V to VCC
0V to VCC
b40 C to a85 C
b55 C to a125 C
Input Rise and Fall Times Devices
(30% to 70% of VCC)
VCC e 3 3V
4 5V
5 5V
10 5 ns max
14 4 ns max
17 6 ns max
Input Rise and Fall Times Devices
(0 8V to 2 0V)
9 6 ns max
Note 1 Absolute maximum ratings are those values beyond which damage
to the device may occur The databook specifications should be met without
exception to ensure that the system design is reliable over its power supply
temperature and output input loading variables National does not recom-
mend operation of CGS circuits outside databook specifications
DC Electrical Characteristics for CGS74C and 54AC Family Devices
Over recommended operating conditions unless specified otherwise
Symbol
Parameter
VCC
(V)
VIH Minimum High Level 3 0
Input Voltage
45
55
VIL Maximum Low Level 3 0
Input Voltage
45
55
VOH Minimum High Level 3 0
Output Voltage
45
(Note 2)
55
CGS74C
TA e a25 C
Typ
15
2 25
2 75
15
2 25
2 75
2 99
4 49
5 49
21
3 15
3 85
09
1 35
1 65
29
44
54
3 0 2 56
4 5 3 86
5 5 4 86
VOL Maximum Low Level 3 0 0 002 0 1
Output Voltage
4 5 0 001 0 1
(Note 2)
5 5 0 001 0 1
3 0 0 36
4 5 0 36
5 5 0 36
54AC
CGS74C
TA e
TA e
b55 C to a125 C b40 C to a85 C
Guaranteed Limits
21 21
3 15 3 15
3 85 3 85
09 09
1 35 1 35
1 65 1 65
29 29
44 44
54 54
2 4 2 46
3 7 3 76
4 7 4 76
01 01
01 01
01 01
0 40 0 44
0 50 0 44
0 50 0 44
Units
V
V
V
V
V
V
Conditions
VOUT e 0 1V
or VCC b0 1V
VOUT e 0 1V
or VCC b0 1V
IOUT e b50 mA
VIN e VIL or VIH
b12 mA
IOH b24 mA
b24 mA
IOUT e 50 mA
VIN e VIL or VIH
12 mA
24 mA
IOL 24 mA
3 http www national com




Part Number 74C2525
Description 1-to-8 Minimum Skew Clock Driver
Maker National Semiconductor
Total Page 10 Pages
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1 74C2525 1-to-8 Minimum Skew Clock Driver National Semiconductor
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