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National Semiconductor Electronic Components Datasheet

74ACQ821L Datasheet

Quiet Series 10-Bit D Flip-Flop with TRI-STATE Outputs

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74ACQ821L pdf
January 1990
Revised September 2000
74ACQ657 74ACTQ657
Quiet SeriesOctal Bidirectional Transceiver with
8-Bit Parity Generator/Checker and 3-STATE Outputs
General Description
The ACQ/ACTQ657 contains eight non-inverting buffers
with 3-STATE outputs and an 8-bit parity generator/
checker. Intended for bus oriented applications, the device
combines the 245 and the 280 functions in one package.
The ACQ/ACTQ utilizes Fairchild Quiet Seriestechnol-
ogy to guarantee quiet output switching and improved
dynamic threshold performance. FACT Quiet Series fea-
tures GTOoutput control and undershoot corrector in
addition to a split ground bus or superior performance.
Features
s Guaranteed simultaneous switching noise level and
dynamic threshold performance
s Guaranteed pin-to-pin skew AC performance
s Combines the 245 and the 280 functions in one package
s 300 mil 24-pin slim dual-in-line package
s Outputs source/sink 24 mA
s ACTQ has TTL-compatible inputs
Ordering Code:
Order Number Package Number
Package Description
74ACQ657SPC
N24C
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
74ACTQ657SC
M24B
24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
74ACTQ657SPC
N24C
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code
Logic Symbols
Connection Diagram
IEEE/IEC
Pin Descriptions
Pin Names
A0A7
B0B7
T/R
OE
PARITY
ODD/EVEN
ERROR
Description
Data Inputs/3-STATE Outputs
Data Inputs/3-STATE Outputs
Transmit/Receive Input
Enable Input
Parity Input/3-STATE Output
ODD/EVEN Parity Input
Error 3-STATE Output
FACT, Quiet Series, FACT Quiet Series, and GTOare trademarks of Fairchild Semiconductor Corporation.
© 2000 Fairchild Semiconductor Corporation DS010636
www.fairchildsemi.com



National Semiconductor Electronic Components Datasheet

74ACQ821L Datasheet

Quiet Series 10-Bit D Flip-Flop with TRI-STATE Outputs

No Preview Available !

74ACQ821L pdf
Functional Description
The Transmit/Receive (T/R) input determines the direction
of the data flow through the bidirectional transceivers.
Transmit (active HIGH) enables data from the A-Port to the
B-Port; Receive (active LOW) enables data from the B-Port
to the A-Port.
The Output Enable (OE) input disables the parity and
ERROR outputs and both the A and B Ports by placing
them in a HIGH-Z condition when the Output Enable input
is HIGH.
When transmitting (T/R HIGH), the parity generator detects
whether an even or odd number of bits on the A-Port are
HIGH and compares these with the condition of the parity
select (ODD/EVEN). If the Parity Select is HIGH and an
even number of A inputs are HIGH, the Parity output is
HIGH.
In receiving mode (T/R LOW), the parity select and number
of HIGH inputs on port B are compared to the condition of
the Parity input. If an even number of bits on the B-Port are
HIGH, the parity select is HIGH, and the PARITY input is
HIGH, then ERROR will be HIGH to indicate no error. If an
odd number of bits on the B-Port are HIGH, the parity
select is HIGH, and the PARITY input is HIGH, the ERROR
will be LOW indicating an error.
Function Table
Number of
Inputs That
Are High
0, 2, 4, 6, 8
1, 3, 5, 7
Immaterial
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
Z = High Impedance
OE
L
L
L
L
L
L
L
L
L
L
L
L
H
Inputs
T/R
H
H
L
L
L
L
H
H
L
L
L
L
X
ODD/EVEN
H
L
H
H
L
L
H
L
H
H
L
L
X
Input/
Output
Parity
H
L
H
L
H
L
L
H
H
L
H
L
Z
Outputs
ERROR
Z
Z
H
L
L
H
Z
Z
L
H
H
L
Z
Outputs Mode
Transmit
Transmit
Receive
Receive
Receive
Receive
Transmit
Transmit
Receive
Receive
Receive
Receive
Z
Function Table
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
Inputs
OE T/R
LL
LH
HX
Outputs
Bus B Data to Bus A
Bus A Data to Bus B
High-Z State
www.fairchildsemi.com
2



National Semiconductor Electronic Components Datasheet

74ACQ821L Datasheet

Quiet Series 10-Bit D Flip-Flop with TRI-STATE Outputs

No Preview Available !

74ACQ821L pdf
Functional Block Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
3 www.fairchildsemi.com




Part Number 74ACQ821L
Description Quiet Series 10-Bit D Flip-Flop with TRI-STATE Outputs
Maker National Semiconductor
Total Page 10 Pages
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74ACQ821L pdf
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