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National Semiconductor Electronic Components Datasheet

74594 Datasheet

8-Bit Shift Register

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74594 pdf
January 1992
MM74HC594 8-Bit Shift Register
with Output Registers
General Description
This high speed shift register utilizes advanced silicon-gate
CMOS technology This device possesses the high noise
immunity and low power consumption of standard CMOS
integrated circuits as well as the ability to drive 15 LS-TTL
loads
This device contains an 8-bit serial-in parallel-out shift reg-
ister that feeds an 8-bit D-type storage register Separate
clocks and direct overriding clears are provided for both the
shift register and the storage register The shift register has
a direct-overriding clear serial input and serial output (stan-
dard) pins for cascading Both the shift register and storage
register use positive-edge triggered clocks If both clocks
are connected together the shift register state will always
be one clock pulse ahead of the storage register
The 54HC 74HC logic family is speed function and pin-out
compatible with the standard 54LS 74LS logic family All
inputs are protected from damage due to static discharge by
internal diode clamps to VCC and ground
Features
Y Low quiescent current 80 mA maximum (74HC Series)
Y Low input current 1 mA maximum
Y 8-bit serial-in parallel-out shift register
with storage
Y Wide operating voltage range 2V – 6V
Y Cascadable
Y Shift register has direct clear
Y Guaranteed shift frequency DC to 30 MHz
Connection Diagram
Truth Table
Dual-In-Line Package
RCK SCK SCLR RCLR
Function
XX
X
L Storage Register cleared
XX
Xu
uX
L
H
H
X Shift Register cleared
Q He
H Shift Register clocked
QNeQnb Q eSER
H Contents of Shift
Register transferred
to output latches
Top View
TL F 10915 – 1
Order Number MM74HC594
See NS Package Number N16E
C1995 National Semiconductor Corporation TL F 10915
RRD-B30M105 Printed in U S A
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National Semiconductor Electronic Components Datasheet

74594 Datasheet

8-Bit Shift Register

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74594 pdf
Absolute Maximum Ratings (Notes 1 2)
Supply Voltage (VCC)
DC Input Voltage (VIN)
DC Output Voltage (VOUT)
Clamp Diode Current (IIK IOK)
DC Output Current per pin (IOUT)
DC VCC or GND Current per pin (ICC)
Storage Temperature Range (TSTG)
Power Dissipation (PD)
(Note 3)
S O Package only
b0 5 to a7 0V
b1 5 to VCCa1 5V
b0 5 to VCCa0 5V
g20 mA
g35 mA
g70 mA
b65 C to a150 C
600 mW
500 mW
Lead Temp (TL) (Soldering 10 seconds)
260 C
Operating Conditions
Supply Voltage VCC
DC Input or Output Voltage
VIN VOUT
Operating Temp Range (TA)
MM HC
Min
b
Max
VCC
a
Units
V
V
C
Input Rise or Fall Times
tr tf VCCe V
VCCe V
VCCe V
ns
ns
ns
DC Electrical Characteristics (Note 4)
Symbol
Parameter
Conditions
VCC
TAe25 C
74HC
TAeb40 to 85 C
Units
Typ Guaranteed Limits
VIH Minimum High Level
Input Voltage
V
V
V
V
V
V
VIL Maximum Low Level
Input Voltage
V
V
V
V
V
V
VOH
Minimum High Level
VINeVIH or VIL
Output Voltage
lIOUTls mA
V
V
V
V
V
V
Q H VINeVIH or VIL
lIOUTls mA
lIOUTls mA
QA thru QH
VINeVIH or VIL
lIOUTls mA
lIOUTls mA
VOL
Maximum Low Level
VINeVIH or VIL
Output Voltage
lIOUTls mA
V
V
V
V
V
V
V
V
V
V
V
V
V
V
Q H VINeVIH or VIL
lIOUTls mA
V
lIOUTls mA
V
QA thru QH
VINeVIH or VIL
lIOUTls mA
lIOUTls mA
V
V
IIN
Maximum Input
VINeVCC or GND
V
Current
gg
V
V
V
V
mA
ICC
Maximum Quiescent
VINeVCC or GND
V
Supply Current
IOUTe mA
mA
Note 1 Absolute Maximum Ratings are those values beyond which damage to the device may occur
Note 2 Unless otherwise specified all voltages are referenced to ground
Note 3 Power Dissipation temperature derating plastic ‘‘N’’ package b12 mW C from 65 C to 85 C ceramic ‘‘J’’ package b12 mW C from 100 C to 125 C
Note 4 For a power supply of 5V g10% the worst case output voltages (VOH and VOL) occur for HC at 4 5V Thus the 4 5V values should be used when
designing with this supply Worst case VIH and VIL occur at VCCe5 5V and 4 5V respectively (The VIH value at 5 5V is 3 85V ) The worst case leakage current (IIN
and ICC) occur for CMOS at the higher voltage and so the 6 0V values should be used
2
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National Semiconductor Electronic Components Datasheet

74594 Datasheet

8-Bit Shift Register

No Preview Available !

74594 pdf
AC Electrical Characteristics VCCe2 0–6 0V CLe50 pF tretfe6 ns (unless otherwise specified)
Symbol
Parameter
Conditions
VCC
TAe25 C
74HC
TAeb40 to 85 C
Units
Typ Guaranteed Limits
fMAX
Maximum Operating
Frequency
CLe pF
V
V
V
MHz
MHz
MHz
tPHL tPLH
Maximum Propagation Delay
from SCK to Q H
CLe pF
V
V
V
ns
ns
ns
tPHL tPLH
Maximum Propagation Delay
from RCK to QA thru QH
tPHL tPLH
Maximum Propagation Delay
from SCLR to Q H
CLe
CLe
CLe
CLe
CLe
CLe
pF
pF
pF
pF
pF
pF
V
V
V
V
V
V
V
V
V
ns
ns
ns
ns
ns
ns
ns
ns
ns
tPHL
Maximum Propagation Delay
from RCLR to QA thru QH
CL e pF
V
V
V
ns
ns
ns
CL e pF
V
V
V
ns
ns
ns
tS SCLR Low to RCK
V
V
V
ns
ns
ns
tS RCLR High to SCK
V
V
V
ns
ns
ns
tS Minimum Setup Time
from SER to SCK
V
V
V
ns
ns
ns
tR Minimum Removal Time
from SCLR to SCK
V
V
V
ns
ns
ns
tS Minimum Setup Time
from SCK to RCK
V
V
V
ns
ns
ns
tH Minimum Hold Time
SER to SCK
V
V
V
ns
ns
ns
tW Minimum Pulse Width
of SCK or SCLR or
RCK or RCLR
V
V
V
ns
ns
ns
tr tf Maximum Input Rise and
Fall Time Clock
V
V
V
ns
ns
ns
tTHL tTLH
tTHL tTLH
CPD
Maximum Output
Rise and Fall Time
QA QH
Maximum Output
Rise and Fall Time
QH
Power Dissipation Capacitance
Outputs Enabled Note
GeVCC
GeGND
V
V
V
V
V
V
ns
ns
ns
ns
ns
ns
pF
pF
CIN
COUT
Maximum Input Capacitance
Maximum Output Capacitance
pF
pF
Note 6 CPD determines the no load dynamic power consumption PDeCPD VCC2 faICC VCC and the no load dynamic current consumption ISeCPD VCC faICC
3
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Part Number 74594
Description 8-Bit Shift Register
Maker National Semiconductor
Total Page 6 Pages
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