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National Semiconductor Electronic Components Datasheet

74F181PC Datasheet

4-Bit Arithmetic Logic Unit

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74F181PC pdf
August 1995
54F 74F181
4-Bit Arithmetic Logic Unit
General Description
The ’F181 is a 4-bit Arithmetic logic Unit (ALU) which can
perform all the possible 16 logic operations on two variables
and a variety of arithmetic operations It is 40% faster than
the Schottky ALU and only consumes 30% as much power
Features
Y Full lookahead for high-speed arithmetic operation on
long words
Y Guaranteed 4000V minimum ESD protection
Commercial
Military
Package
Number
Package Description
74F181PC
N24A
24-Lead (0 600 Wide) Molded Dual-In-Line
74F181SPC
N24C
24-Lead (0 300 Wide) Molded Dual-In-Line
54F181DM (Note 2)
J24A
24-Lead Ceramic Dual-In-Line
54F181SDM (Note 2)
J24F
24-Lead (0 300 ) Ceramic Dual-In-Line
74F181SC (Note 1)
M24B
24-Lead (0 300 ) Molded Small Outline JEDEC
54F181FM (Note 2)
W24C
24-Lead Cerpack
54F181LM (Note 2)
E28A
24-Lead Ceramic Leadless Chip Carrier Type C
Note 1 Devices also available in 13 reel Use suffix e SCX
Note 2 Military grade device with environmental and burn-in processing Use suffix e DMQB FMQB and LMQB
Connection Diagrams
Pin Assignment
for DIP SOIC and Flatpak
Pin Assignment
for LCC
TL F 9491 – 1
TRI-STATE is a registered trademark of National Semiconductor Corporation
C1995 National Semiconductor Corporation TL F 9491
TL F 9491 – 2
RRD-B30M105 Printed in U S A


National Semiconductor Electronic Components Datasheet

74F181PC Datasheet

4-Bit Arithmetic Logic Unit

No Preview Available !

74F181PC pdf
Logic Symbols
Active-HIGH Operands
Active-LOW Operands
IEEE IEC
TL F 9491–3
TL F 9491 – 4
Unit Loading Fan Out
54F 74F
Pin Names
Description
U L Input IIH IIL
HIGH LOW Output IOH IOL
A0 – A3
B0 – B3
S0 – S3
M
Cn
F0 – F3
AeB
G
P
Cn a 4
A Operand Inputs (Active LOW)
B Operand Inputs (Active LOW)
Function Select Inputs
Mode Control Input
Carry Input
Function Outputs (Active LOW)
Comparator Output
Carry Generate Output (Active LOW)
Carry Propagate Output (Active LOW)
Carry Output
10 30
10 30
10 40
10 10
10 50
50 33 3
OC 33 3
50 33 3
50 33 3
50 33 3
20 mA b1 8 mA
20 mA b1 8 mA
20 mA b2 4 mA
20 mA b0 6 mA
20 mA b3 0 mA
b1 mA 20 mA
20 mA
b1 mA 20 mA
b1 mA 20 mA
b1 mA 20 mA
OC-Open Collector
TL F 9491 – 10
Functional Description
The ’F181 is a 4-bit high-speed parallel Arithmetic Logic
Unit (ALU) Controlled by the four Function Select inputs
(S0 – S3) and the Mode Control input (M) it can perform all
the 16 possible logic operations or 16 different arithmetic
operations on Active HIGH or Active LOW operands The
Function Table lists these operations
When the Mode Control input (M) is HIGH all internal car-
ries are inhibited and the device performs logic operations
on the individual bits as listed When the Mode Control input
is LOW the carries are enabled and the device performs
arithmetic operations on the two 4-bit words The device
incorporates full internal carry lookahead and provides for
either ripple carry between devices using the Cn a 4 output
or for carry lookahead between packages using the signals
P (Carry Propagate) and G (Carry Generate) In the Add
mode P indicates that F is 15 or more while G indicates
that F is 16 or more In the Subtract mode P indicates that F
is zero or less while G indicates that F is less than zero P
and G are not affected by carry in When speed require-
ments are not stringent the ’F181 can be used in a simple
Ripple Carry mode by connecting the Carry output (Cna4)
signal to the Carry input (Cn) of the next unit For high speed
operation the device is used in conjunction with a carry look-
ahead circuit One carry lookahead package is required for
each group of four ’F181 devices Carry lookahead can be
provided at various levels and offers high speed capability
over extremely long word lengths
The AeB output from the device goes HIGH when all four F
outputs are HIGH and can be used to indicate logic equiva-
lence over four bits when the unit is in the Subtract mode
The AeB output is open collector and can be wired AND
with other AeB outputs to give a comparison for more than
four bits The AeB signal can also be used with the Cna4
signal to indicate AlB and AkB
The Function Table lists the arithmetic operations that are
performed without a carry in An incoming carry adds a one
to each operation Thus select code LHHL generates A
minus B minus 1 (2s complement notation) without a carry
in and generates A minus B when a carry is applied Be-
cause subtraction is actually performed by complementary
addition (1s complement) a carry out means borrow thus a
carry is generated when there is no underflow and no carry
is generated when there is underflow As indicated this de-
vice can be used with either active LOW inputs producing
active LOW outputs or with active HIGH inputs producing
active HIGH outputs For either case the table lists the oper-
ations that are performed to the operands labeled inside the
logic symbol
2


Part Number 74F181PC
Description 4-Bit Arithmetic Logic Unit
Maker National
Total Page 10 Pages
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