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NXP Semiconductors Electronic Components Datasheet

VCH162373ADGG Datasheet

16-bit D-type transparent latch with 30 ohm series termination resistors; 5 V input/output tolerant; 3-state

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VCH162373ADGG pdf
INTEGRATED CIRCUITS
DATA SHEET
74LVC162373A; 74LVCH162373A
16-bit D-type transparent latch with
30 series termination resistors;
5 V input/output tolerant; 3-state
Product specification
File under Integrated Circuits, IC24
1999 Aug 05


NXP Semiconductors Electronic Components Datasheet

VCH162373ADGG Datasheet

16-bit D-type transparent latch with 30 ohm series termination resistors; 5 V input/output tolerant; 3-state

No Preview Available !

VCH162373ADGG pdf
Philips Semiconductors
Product specification
16-bit D-type transparent latch with 30 series
74LVC162373A;
termination resistors; 5 V input/output tolerant; 3-state 74LVCH162373A
FEATURES
ESD protection:
HBM EIA/JESD22-A114-A
exceeds 2000 V
MM EIA/JESD22-A115-A
exceeds 200 V
5 V tolerant input/output for
interfacing with 5 V logic
Wide supply voltage range of
1.2 to 3.6 V
Complies with JEDEC standard
no. 8-1A
CMOS low power consumption
MULTIBYTEflow-through
standard pin-out architecture
Low inductance multiple power and
ground pins for minimum noise and
ground bounce
Direct interface with TTL levels
All data inputs have bus hold
(74LVCH162373A only)
High impedance when VCC = 0
Power off disables outputs,
permitting live insertion.
DESCRIPTION
The 74LVC(H)162373A is a 16-bit D-type transparent latch featuring separate
D-type inputs for each latch and 3-state outputs for bus oriented applications.
One latch enable (LE) input and one output enable (OE) are provide for each
octal. Inputs can be driven from either 3.3 or 5 V devices. In 3-state operation,
outputs can handle 5 V. These features allow the use of these devices in a
mixed 3.3 and 5 V environment.
The 74LVC(H)162373 consists of 2 sections of eight D-type transparent latches
with 3-state true outputs. When LE is HIGH, data at the Dn inputs enter the
latches. In this condition the latches are transparent, i.e. a latch output will
change each time its corresponding D-input changes.
When LE is LOW the latches store the information that was present at the
D-inputs a set-up time preceding the HIGH-to-LOW transition of LE.
When OE is LOW, the contents of the eight latches are available at the outputs.
When OE is HIGH, the outputs go to the high-impedance OFF-state.
Operation of the OE input does not affect the state off latches.
The 74LVCH162373A bus hold data inputs eliminates the need for external pull
up resistors to hold unused inputs.
The 74LVC(H)162373A is designed with 30 series termination resistors in
both HIGH and LOW output stages to reduce line noise.
FUNCTION TABLE (per section of eight bits)
See note 1.
OPERATION MODES
Enable and read register
(transparent mode)
Latch and read register
Latch register and disable outputs
INPUTS
OE LE Dn
LHL
LHH
LL
l
LLh
HL
l
HL h
INTERNAL
LATCHES
L
H
L
H
L
H
Note
1. H = HIGH voltage level;
h = HIGH voltage level one set-up time prior to the HIGH-to-LOW LE transition;
L = LOW voltage level;
l = LOW voltage level one set-up time prior to the HIGH-to-LOW LE transition;
Z = high-impedance OFF-state.
OUTPUTS
Q0 to Q7
L
H
L
H
Z
Z
1999 Aug 05
2


Part Number VCH162373ADGG
Description 16-bit D-type transparent latch with 30 ohm series termination resistors; 5 V input/output tolerant; 3-state
Maker NXP
Total Page 16 Pages
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