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NXP Semiconductors Electronic Components Datasheet

80C554 Datasheet

80C51 8-bit microcontroller . 6 clock operation 16K/512 OTP/ROM/ROMless/ 7 channel 10 bit A/D/ I2C/ PWM/ capture/compare/ high I/O/ 64L LQFP

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80C554 pdf
INTEGRATED CIRCUITS
80C554/83C554/87C554
80C51 8-bit microcontroller – 6 clock operation
16K/512 OTP/ROM/ROMless, 7 channel 10 bit A/D, I2C,
PWM, capture/compare, high I/O, 64L LQFP
Preliminary specification
Replaces data of 1999 Apr 07
IC20 Data Handbook
2000 Nov 10
Philips
Semiconductors



NXP Semiconductors Electronic Components Datasheet

80C554 Datasheet

80C51 8-bit microcontroller . 6 clock operation 16K/512 OTP/ROM/ROMless/ 7 channel 10 bit A/D/ I2C/ PWM/ capture/compare/ high I/O/ 64L LQFP

No Preview Available !

80C554 pdf
Philips Semiconductors
80C51 8-bit microcontroller – 6 clock operation
16K/512 OTP/ROM/ROMless, 7 channel 10 bit A/D, I2C, PWM,
capture/compare, high I/O, 64L LQFP
Preliminary specification
80C554/83C554/87C554
DESCRIPTION
This data sheet describes the 6 clock version of the 8xC554. This
device is only available in 64L LQFP. The 8xC554 Single-Chip 8-Bit
Microcontroller is manufactured in an advanced CMOS process and
is a derivative of the 80C51 microcontroller family. The 87C554 has
the same instruction set as the 80C51. Three versions of the
derivative exist:
83C554—16k bytes ROM
80C554—ROMless version
87C554—16k bytes EPROM
The 87C554 contains a 16k × 8 non-volatile EPROM, a 512 × 8
read/write data memory, five 8-bit I/O ports, one 8-bit input port, two
16-bit timer/event counters (identical to the timers of the 80C51), an
additional 16-bit timer coupled to capture and compare latches, a
15-source, four-priority-level, nested interrupt structure, an 7-input
ADC, a dual DAC pulse width modulated interface, two serial
interfaces (UART and I2C-bus), a “watchdog” timer and on-chip
oscillator and timing circuits. For systems that require extra
capability, the 8xC554 can be expanded using standard TTL
compatible memories and logic.
In addition, the 8xC554 has two software selectable modes of power
reduction—idle mode and power-down mode. The idle mode freezes
the CPU while allowing the RAM, timers, serial ports, and interrupt
system to continue functioning. Optionally, the ADC can be operated
in Idle mode. The power-down mode saves the RAM contents but
freezes the oscillator, causing all other chip functions to be
inoperative.
The device also functions as an arithmetic processor having
facilities for both binary and BCD arithmetic plus bit-handling
capabilities. The instruction set consists of over 100 instructions:
49 one-byte, 45 two-byte, and 17 three-byte. With an 8 MHz crystal,
58% of the instructions are executed in 0.75 µs and 40% in 1.5 µs.
Multiply and divide instructions require 3 µs.
FEATURES
80C51 central processing unit
16k × 8 EPROM expandable externally to 64k bytes
An additional 16-bit timer/counter coupled to four capture registers
and three compare registers
Two standard 16-bit timer/counters
512 × 8 RAM, expandable externally to 64k bytes
Capable of producing eight synchronized, timed outputs
A 10-bit ADC with seven multiplexed analog inputs
Fast 8-bit ADC option – 9 µS at 16 MHz
Two 8-bit resolution, pulse width modulation outputs
Five 8-bit I/O ports plus one 8-bit input port shared with analog
inputs
I2C-bus serial I/O port with byte oriented master and slave
functions
On-chip watchdog timer
Extended temperature ranges
Full static operation – 0 to 16 MHz
Operating voltage range: 2.7 V to 5.5 V (0 to 8 MHz) and
4.5 V to 5.5 V (8 to 16 MHz) commercial temperature
Security bits:
– ROM – 2 bits
– OTP/EPROM – 3 bits
4 level priority interrupt
15 interrupt sources
Full-duplex enhanced UART
– Framing error detection
– Automatic address recognition
Power control modes
– Clock can be stopped and resumed
– Idle mode
– Power down mode
Second DPTR register
EMI reduction – 6 clock operation and ALE inhibit
Programmable I/O pins
Wake-up from power-down by external interrupts
Software reset
Power-on detect reset
ADC charge pump disable
ONCE mode
ADC active in Idle mode
2000 Nov 10
2



NXP Semiconductors Electronic Components Datasheet

80C554 Datasheet

80C51 8-bit microcontroller . 6 clock operation 16K/512 OTP/ROM/ROMless/ 7 channel 10 bit A/D/ I2C/ PWM/ capture/compare/ high I/O/ 64L LQFP

No Preview Available !

80C554 pdf
Philips Semiconductors
80C51 8-bit microcontroller – 6 clock operation
16K/512 OTP/ROM/ROMless, 7 channel 10 bit A/D, I2C, PWM,
capture/compare, high I/O, 64L LQFP
Preliminary specification
80C554/83C554/87C554
ORDERING INFORMATION
OTP/EPROM
ROM
P87C554SBBD
P83C554SBBD
P87C554SFBD
P83C554SFBD
ROMless
P80C554SBBD
P80C554SFBD
TEMPERATURE °C AND PACKAGE
0 to +70, Low Profile Quad Flat Package
–40 to +85, Low Profile Quad Flat
Package
FREQ.
(MHz)
16
16
DRAWING
NUMBER
SOT314–2
SOT314–2
PART NUMBER DERIVATION
DEVICE NUMBER
OPERATING FREQUENCY MAX
P87C554 OTP
P83C554 ROM
S = 16 MHz
P80C554 ROMless
TEMPERATURE RANGE
B= 0_C to 70_C
F = –40_C to +85_C
PACKAGE
BD=64L LQFP
BLOCK DIAGRAM
T0 T1
33
INT0 INT1
33
VDD
VSS
PWM0
PWM1
AVSS AVREF ADC0-7 SDA SCL
–+
AVDD STADC
51 1
XTAL1
XTAL2
EA
ALE
PSEN
3
WR
3
RD
0
AD0-7
2
A8-15
T0, T1
TWO 16-BIT
TIMER/EVENT
COUNTERS
CPU
80C51 CORE
EXCLUDING
ROM/RAM
PARALLEL I/O
PORTS AND
EXTERNAL BUS
SERIAL
UART
PORT
PROGRAM
MEMORY
16k x 8
OTP/ROM
DATA
MEMORY
512 x 8 RAM
DUAL
PWM
ADC
SERIAL
I2C PORT
8-BIT INTERNAL BUS
16
8-BIT
PORT
FOUR
16-BIT
CAPTURE
LATCHES
T2
16-BIT
TIMER/
EVENT
COUNTERS
16
T2
16-BIT
COMPARA-
TORS
WITH
REGISTERS
COMPARA-
TOR
OUTPUT
SELECTION
T3
WATCHDOG
TIMER
33
P0 P1 P2 P3 TxD RxD
P5 P4
1
CT0I-CT3I
1
T2
1
RT2
0 ALTERNATE FUNCTION OF PORT 0
1 ALTERNATE FUNCTION OF PORT 1
2 ALTERNATE FUNCTION OF PORT 2
3 ALTERNATE FUNCTION OF PORT 3
4 ALTERNATE FUNCTION OF PORT 4
5 ALTERNATE FUNCTION OF PORT 5
4
CMSR0-CMSR5 RST EW
CMT0, CMT1
SU00951
2000 Nov 10
3




Part Number 80C554
Description 80C51 8-bit microcontroller . 6 clock operation 16K/512 OTP/ROM/ROMless/ 7 channel 10 bit A/D/ I2C/ PWM/ capture/compare/ high I/O/ 64L LQFP
Maker NXP
Total Page 30 Pages
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