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NXP Semiconductors Electronic Components Datasheet

74AUP1G86 Datasheet

Low Power 2-Input EXCLUSIVE-OR Gate

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74AUP1G86
Low-power 2-input EXCLUSIVE-OR gate
Rev. 01 — 9 August 2004
Product data sheet
1. General description
The 74AUP1G86 is a high-performance, low-power, low-voltage, Si-gate CMOS device,
superior to most advanced CMOS compatible TTL families.
Schmitt-trigger action at all inputs makes the circuit tolerant to slower input rise and fall
times across the entire VCC range from 0.8 V to 3.6 V.
This device ensures a very low static and dynamic power consumption across the entire
VCC range from 0.8 V to 3.6 V.
This device is fully specified for partial Power-down applications using IOFF.
The IOFF circuitry disables the output, preventing the damaging backflow current through
the device when it is powered down.
The 74AUP1G86 provides the single 2-input EXCLUSIVE-OR function.
2. Features
s Wide supply voltage range from 0.8 V to 3.6 V
s High noise immunity
s Complies with JEDEC standards:
x JESD8-12 (0.8 V to 1.3 V)
x JESD8-11 (0.9 V to 1.65 V)
x JESD8-7 (1.2 V to 1.95 V)
x JESD8-5 (1.8 V to 2.7 V)
x JESD8-B (2.7 V to 3.6 V)
s ESD protection:
x HBM JESD22-A114-C exceeds 2000 V
x MM JESD22-A115-A exceeds 200 V
x CDM JESD22-C101-C exceeds 1000 V
s Low static power consumption; ICC = 0.9 µA (maximum)
s Latch-up performance exceeds 100 mA per JESD 78 Class II
s Inputs accept voltages up to 3.6 V
s Low noise overshoot and undershoot < 10 % of VCC
s IOFF circuitry provides partial Power-down mode operation
s Multiple package options
s Specified from 40 °C to +85 °C and 40 °C to +125 °C


NXP Semiconductors Electronic Components Datasheet

74AUP1G86 Datasheet

Low Power 2-Input EXCLUSIVE-OR Gate

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74AUP1G86 pdf
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Philips Semiconductors
74AUP1G86
Low-power 2-input EXCLUSIVE-OR gate
3. Quick reference data
Table 1: Quick reference data
GND = 0 V; Tamb = 25 °C; tr = tf 3 ns.
Symbol Parameter
Conditions
tPHL, tPLH propagation delay
A or B to Y
CL = 5 pF; RL = 1 M;
VCC = 0.8 V
CL = 5 pF; RL = 1 M;
VCC = 1.1 V to 1.3 V
CL = 5 pF; RL = 1 M;
VCC = 1.4 V to 1.6 V
CL = 5 pF; RL = 1 M;
VCC = 1.65 V to 1.95 V
CL = 5 pF; RL = 1 M;
VCC = 2.3 V to 2.7 V
CL = 5 pF; RL = 1 M;
VCC = 3.0 V to 3.6 V
Ci input capacitance
CPD power dissipation VCC = 1.8 V; f = 10 MHz
capacitance
VCC = 3.3 V; f = 10 MHz
Min
-
2.3
1.8
1.5
1.2
1.0
-
[1] [2] -
[1] [2] -
[1] CPD is used to determine the dynamic power dissipation (PD in µW).
PD = CPD × VCC2 × fi × N + Σ(CL × VCC2 × fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in V;
N = number of inputs switching;
Σ(CL × VCC2 × fo) = sum of the outputs.
[2] The condition is VI = GND to VCC.
4. Ordering information
Typ Max Unit
21.2 -
ns
5.9 13.1 ns
4.1 7.7 ns
3.3 5.9 ns
2.6 4.4 ns
2.3 4.0 ns
0.8 -
3.7 -
4.5 -
pF
pF
pF
Table 2: Ordering information
Type number
Package
Temperature range Name
74AUP1G86GW 40 °C to +125 °C TSSOP5
74AUP1G86GM 40 °C to +125 °C XSON6
Description
Version
plastic thin shrink small outline package; 5 leads;
body width 1.25 mm
SOT353-1
plastic extremely thin small outline package; no leads; SOT886
6 terminals; body 1 × 1.45 × 0.5 mm
5. Marking
Table 3: Marking
Type number
74AUP1G86GW
74AUP1G86GM
Marking code
pH
pH
9397 750 14684
Product data sheet
Rev. 01 — 9 August 2004
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
2 of 16


Part Number 74AUP1G86
Description Low Power 2-Input EXCLUSIVE-OR Gate
Maker NXP
Total Page 16 Pages
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