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NXP Semiconductors Electronic Components Datasheet

74ABT544N Datasheet

Octal latched transceiver with dual enable/ inverting 3-State

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74ABT544N pdf
Philips Semiconductors Advanced BiCMOS Products
Octal latched transceiver with dual enable,
inverting (3-State)
Product specification
74ABT544
FEATURES
Combines 74ABT245 and 74ABT373 type
functions in one device
8-bit octal transceiver with D-type latch
Back-to-back registers for storage
Separate controls for data flow in each
direction
Output capability: +64mA/–32mA
Live insertion/extraction permitted
Power-up 3-State
Power-up reset
Latch-up protection exceeds 500mA per
Jedec JC40.2 Std 17
ESD protection exceeds 2000 V per MIL
STD 883 Method 3015 and 200 V per
Machine Model
DESCRIPTION
The 74ABT544 high-performance BiCMOS
device combines low static and dynamic
power dissipation with high speed and high
output drive.
The 74ABT544 Octal Registered Transceiver
contains two sets of D-type latches for
temporary storage of data flowing in either
direction. Separate Latch Enable (LEAB,
LEBA) and Output Enable (OEAB, OEBA)
inputs are provided for each register to
permit independent control of data transfer in
either direction. The outputs are guaranteed
to sink 64mA.
FUNCTIONAL DESCRIPTION
The ’ABT544 contains two sets of eight
D–type latches, with separate control pins for
each set. Using data flow from A to B as an
example, when the A-to-B Enable (EAB)
input and the A-to-B Latch Enable (LEAB)
input are Low the A-to-B path is transparent.
A subsequent Low-to-High transition of the
LEAB signal puts the A data into the latches
where it is stored and the B outputs no longer
change with the A inputs. With EAB and
OEAB both Low, the 3-State B output buffers
are active and invert the data present at the
outputs of the A latches.
Control of data flow from B to A is similar, but
using the EBA, LEBA, and OEBA inputs.
ORDERING INFORMATION
PACKAGES
24-pin plastic DIP
24-pin plastic SOL
24-pin plastic SSOP Type II
TEMPERATURE RANGE
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
ORDER CODE
74ABT544N
74ABT544D
74ABT544DB
DRAWING NUMBER
0410D
0173D
1641A
PIN CONFIGURATION
LEBA 1
OEBA 2
A0 3
A1 4
A2 5
A3 6
A4 7
A5 8
A6 9
A7 10
EAB 11
GND 12
24 VCC
23 EBA
22 B0
21 B1
20 B2
19 B3
18 B4
17 B5
16 B6
15 B7
14 LEAB
13 OEAB
June 1, 1993
LOGIC SYMBOL
LOGIC SYMBOL (IEEE/IEC)
3 4 5 6 7 8 9 10
A0 A1 A2 A3 A4 A5 A6 A7
11 EAB
23 EBA
14 LEAB
1 LEBA
OEAB
OEBA
13
2
B0 B1 B2 B3 B4 B5 B6 B7
22 21 20 19 18 17 16 15
2 1EN3 (AB)
23 G1
1
1C5
13
2EN4 (BA)
11
G2
14
2C6
3
3
5D
4
5D 4
5
6
7
8
9
10
22
21
20
19
18
17
16
15
1 853–1610 09907


NXP Semiconductors Electronic Components Datasheet

74ABT544N Datasheet

Octal latched transceiver with dual enable/ inverting 3-State

No Preview Available !

74ABT544N pdf
Philips Semiconductors Advanced BiCMOS Products
Octal latched transceiver with dual enable,
inverting (3-State)
Product specification
74ABT544
PIN DESCRIPTION
PIN NUMBER
14, 1
11, 23
13, 2
3, 4, 5, 6,
7, 8, 9, 10
22, 21, 20, 19,
18, 17, 16, 15
12
24
SYMBOL
LEAB / LEBA
EAB / EBA
OEAB / OEBA
A0 – A7
B0 – B7
GND
VCC
FUNCTION
A to B / B to A Latch Enable input (active-Low)
A to B / B to A Enable input (active-Low)
A to B / B to A Output Enable input (active-Low)
Port A, 3-State outputs
Port B, 3-State outputs
Ground (0V)
Positive supply voltage
QUICK REFERENCE DATA
SYMBOL
PARAMETER
tPLH
tPHL
CIN
CI/O
ICCZ
Propagation delay
An to Bn or Bn to An
Input capacitance
I/O capacitance
Total supply current
CONDITIONS
Tamb = 25°C; GND = 0V
CL = 50pF; VCC = 5V
VI = 0V or VCC
Outputs disabled;
VO = 0V or VCC
Outputs disabled; VCC = 5.5V
TYPICAL
3.9
4
7
110
UNIT
ns
pF
pF
µA
June 1, 1993
2


Part Number 74ABT544N
Description Octal latched transceiver with dual enable/ inverting 3-State
Maker NXP
Total Page 8 Pages
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