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74ABT16501A Datasheet

18-bit universal bus transceiver 3-State

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74ABT16501A pdf
INTEGRATED CIRCUITS
74ABT16501A
74ABTH16501A
18-bit universal bus transceiver (3-State)
Product specification
Supersedes data of 1997 Jun 12
IC23 Data Handbook
1998 Feb 27
Philips
Semiconductors


NXP Semiconductors Electronic Components Datasheet

74ABT16501A Datasheet

18-bit universal bus transceiver 3-State

No Preview Available !

74ABT16501A pdf
Philips Semiconductors
18-bit universal bus transceiver (3-State)
Product specification
74ABT16501A
74ABTH16501A
FEATURES
18-bit bidirectional bus interface
3-State buffers
Output capability: +64mA/-32mA
TTL input and output switching levels
74ABTH16501A incorporates bus-hold data inputs which
eliminate the need for external pull-up resistors to hold unused
inputs
Live insertion/extraction permitted
Power-up reset
Power-up 3-State
Positive edge-triggered clock inputs
Latch-up protection exceeds 500mA per JEDEC Std 17
ESD protection exceeds 2000V per MIL STD 883 Method 3015
and 200V per Machine Model
Flexible operation permits 18 embedded D-type latches or
flip-flops to operate in clocked, transparent, and latched modes.
QUICK REFERENCE DATA
DESCRIPTION
The 74ABT16501A high-performance BiCMOS device combines low
static and dynamic power dissipation with high speed and high
output drive.
This device is an 18-bit universal transceiver featuring non-inverting
3-State bus compatible outputs in both send and receive directions.
Data flow in each direction is controlled by output enable (OEAB and
OEBA), latch enable (LEAB and LEBA), and clock (CPAB and
CPBA) inputs. For A-to-B data flow, the device operates in the
transparent mode when LEAB is High. When LEAB is Low, the A
data is latched if CPAB is held at a High or Low logic level. If LEAB
is Low, the A-bus data is stored in the latch/flip-flop on the
Low-to-High transition of CPAB. When OEAB is High, the outputs
are active. When OEAB is Low, the outputs are in the
high-impedance state.
Data flow for B-to-A is similar to that of A-to-B but uses OEBA,
LEBA and CPBA. The output enables are complimentary (OEAB is
active High, and OEBA is active Low).
Active bus-hold circuitry is provided to hold unused or floating data
inputs at a valid logic level.
Two options are available, 74ABT16501A which does not have the
bus-hold feature and 74ABTH16501A which incorporates the
bus-hold feature.
SYMBOL
tPLH
tPHL
CIN
CI/O
ICCZ
ICCL
PARAMETER
Propagation delay
An to Bn or Bn to An
Input capacitance (Control pins)
I/O pin capacitance
Quiescent supply current
CONDITIONS
Tamb = 25°C; GND = 0V
CL = 50pF;
VCC = 5V
VI = 0V or VCC
Outputs disabled; VI/O = 0V or VCC
Outputs disabled; VCC = 5.5V
Outputs low; VCC = 5.5V
TYPICAL
2.2
1.8
3
7
500
9
UNIT
ns
pF
pF
µA
mA
ORDERING INFORMATION
PACKAGES
56-Pin Plastic SSOP Type III
56-Pin Plastic TSSOP Type II
56-Pin Plastic SSOP Type III
56-Pin Plastic TSSOP Type II
TEMPERATURE RANGE
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
OUTSIDE NORTH AMERICA
74ABT16501A DL
74ABT16501A DGG
74ABTH16501A DL
74ABTH16501A DGG
NORTH AMERICA
BT16501A DL
BT16501A DGG
BH16501A DL
BH16501A DGG
DWG NUMBER
SOT371-1
SOT364-1
SOT371-1
SOT364-1
1998 Feb 27
2 853-1788 19027


Part Number 74ABT16501A
Description 18-bit universal bus transceiver 3-State
Maker NXP
Total Page 13 Pages
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