MOS INTEGRATED CIRCUIT
32M-WORD BY 64-BIT SYNCHRONOUS DYNAMIC RAM MODULE
The MC-4532CD647EF and MC-4532CD647PF are 33,554,432 words by 64 bits synchronous dynamic RAM
module on which 16 pieces of 128M SDRAM: µPD45128841 are assembled.
This module provides high density and large quantities of memory in a small space without utilizing the surface-
mounting technology on the printed circuit board.
Decoupling capacitors are mounted on power supply line for noise reduction.
• 33,554,432 words by 64 bits organization
• Clock frequency and access time from CLK.
Access time from CLK
CL = 3
CL = 2
CL = 3
CL = 2
• Fully Synchronous Dynamic RAM, with all signals referenced to a positive clock edge
• Pulsed interface
• Possible to assert random column address in every cycle
• Quad internal banks controlled by BA0 and BA1 (Bank Select)
• Programmable burst-length (1, 2, 4, 8 and full page)
• Programmable wrap sequence (Sequential / Interleave)
5 • Programmable /CAS latency (2, 3)
• Automatic precharge and controlled precharge
• CBR (Auto) refresh and self refresh
• All DQs have 10 Ω ±10 % of series resistor
• Single 3.3 V ± 0.3 V power supply
• LVTTL compatible
• 4,096 refresh cycles/64 ms
• Burst termination by Burst Stop command and Precharge command
• 168-pin dual in-line memory module (Pin pitch = 1.27 mm)
• Unbuffered type
• Serial PD
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
Document No. M14276EJ2V0DS00 (2nd edition)
Date Published January 2000 NS CP(K)
Printed in Japan
The mark • shows major revised points.