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  NEC Electronic Components Datasheet  

J133-Z Datasheet

P-CHANNEL POWER MOS FET

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J133-Z pdf
DATA SHEET
MOS FIELD EFFECT POWER TRANSISTORS
2SJ133, 2SJ133-Z
P-CHANNEL POWER MOS FET
FOR SWITCHING
FEATURES
• Gate drive available at logic level (VGS = –4 V)
• High current control available in small
dimension due to low RDS(on) (0.45 )
• 2SJ133-Z is a lead process product and is deal
for mounting a hybrid IC.
QUALITY GRADES
• Standard
Please refer to “Quality Grades on NEC
Semiconductor Devices” (Document No.
C11531E) published by NEC Corporation to
know the specification of quality grade on the
devices and its recommended applications.
ABSOLUTE MAXIMUM RATINGS (Ta = 25°C)
Parameter
Symbol
Conditions
Drain to source voltage
VDSS
VGS = 0
Gate to source voltage
VGSS
VDS = 0
Drain current (DC)
Drain current (pulse)
ID(DC)
ID(pulse)
TC = 25°C
PW 300 µs
duty cycle 10 %
Total power dissipation
PT TC = 25°C
Total power dissipation
PT Ta = 25°C
Channel temperature
Tch
Storage temperature
Tstg
* Printing board mounted
** 7.5 cm2 × 0.7 mm ceramic board mounted
PACKAGE DRAWING (UNIT: mm)
Ratings
60
+–20
+–2.0
+–8.0
Electrode connection
<1> Gate (G)
<2> Drain (D)
<3> Source (S)
<4> Fin (drain)
Unit INTERNAL
EQUIVALENT CIRCUIT
V
V
A
A
20
1.0*, 2.0**
150
55 to +150
W
W
°C
°C
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
Document No. D16193EJ2V0DS00 (2nd edition)
Date Published April 2002 N CP(K)
Printed in Japan
©
21090928


  NEC Electronic Components Datasheet  

J133-Z Datasheet

P-CHANNEL POWER MOS FET

No Preview Available !

J133-Z pdf
2SJ133, 2SJ133-Z
ELECTRICAL CHARACTERISTICS (Ta = 25°C)
Parameter
Drain cutoff current
Gate cutoff current
Gate cutoff voltage
Forward transfer
admittance
Drain to source on-state
resistance
Drain to source on-state
resistance
Input capacitance
Output capacitance
Reverse transfer
capacitance
Turn-on delay time
Rise time
Turn-off delay time
Fall time
Symbol
IDSS
IGSS
VGS(off)
yts
Conditions
VDS = 60 V, VGS = 0
VGS = +–20 V, VDS = 0
VDS = 10 V, ID = 1.0 mA
VDS = 10 V, ID = 1.0 A
RDS(on)1 VGS = 10 V, ID = 1.0 A
RDS(on)2 VGS = 4 V, ID = 0.8 A
Ciss
Coss
Crss
VDS = 10 V, VGS = 0 V
f = 1 MHz
td(on)
tr
td(off)
tf
ID = 1.0 A, VGS(on) = 10 V
VDD ≅ −30 V, RL = 30 ,
Rin = 10
MIN.
1.0
1.0
TYP.
2.0
1.8
MAX.
10
+–100
3.0
Unit
µA
nA
V
S
0.45 0.8
0.7 1.3
660 pF
250 pF
50 pF
30 ns
30 ns
110 ns
40 ns
SWITCHING TIME TEST CIRCUIT, TEST CONDITION (RESISTANCE LOAD)
2 Data Sheet D16193EJ2V0DS


Part Number J133-Z
Description P-CHANNEL POWER MOS FET
Maker NEC
Total Page 6 Pages
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