MOS INTEGRATED CIRCUIT
LSI DEVICES FOR Inter Equipment BusTM (IEBusTM)
The µPD72042 is a microcomputer peripheral LSI device for IEBus protocol control.
The µPD72042 performs all the processing required for layers 1 and 2 of the IEBus. The devices incorporate large
transmission and reception buffers, allowing the microcomputer to perform IEBus operations without interruption.
They also contain an IEBus driver and receiver, allowing them to directly connected to the bus directly.
• Control of layers 1 and 2 of the IEBus protocol
• Support of a multi-master scheme
• Broadcast function
• Two communication modes having different
transmission speeds can be selected.
Approx. 3.9 Kbps
Approx. 17 Kbps
q Built-in IEBus driver and receiver
q Transmission and reception buffers
Transmission buffer : 33 bytes, FIFO
: 40 bytes, FIFO (capable of
holding more than one frame
of reception data.)
• Microcomputer interface
Three-/two-wire serial I/O,
Transfer starting with MSB
• Program crashes can be detected by means of a
• Low power consumption (standby mode):
50 µA (max)
• Oscillator frequency (fX): 6 MHz
• frequency accuracy: ±1.5%
• Operating voltage: 5 V ±10%
16-pin plastic SOP (9.53 mm (375))
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for availability
and additional information.
Document No. S14870EJ1V0DS00 (1st edition)
Date Published June 2000 N CP(N)
Printed in Japan