MCM69Q618 Datasheet | Motorola Semiconductor

MOTOROLA SEMICONDUCTOR TECHNICAL DATA Order this document by MCM69Q618/D Advance Information 64K x 18 Bit Synchronous Separate I/O Fast SRAM The Motorola MCM69Q618 is a 1 Megabit static random access memory, organized as 64K words of 18 bits. It Features separate data input and data output buffers and incorporates input and output registers on board with high speed SRAM. The MCM69Q618 allows the user to perform transparent write and data pass through. Two data bus ports are provided - a data input (D) and a data output (Q) port. The synchronous design allows for precise cycle control with the use of an external single clock (K). Address port, data input (D0 - D17), data output (Q0 - Q17), write enable (W), chip enables (E1, E2), and pass- through enable (PT) are registered on the rising edge of clock (K). Any given cycle operates on only one address. However, for any cycle, reads and writes can be intermixed. Thus, one can perform a read, a write, or a bination read/ write during any one cycle. For a bination read/write, the contents of the array are read before the new data is written. By using the pass- through function, the output port Q can be made to reflect either the contents of the array or the data presented to the input port D. For read/write or a read cycle with G low, the Q port will output the contents of the array. However, if PT is asserted, the Q port will instead output the data presented at the D input port. - - - - - - - - - - - - - - Single 3.3 V ± 5% Power Supply Fast Access Times: 6/8/10 ns Max Sustained Throughput of 1.49 Gigabits/Second Single Clock Operation Address, Data Input, E1, E2, PT, W, and Data Output Registers on Chip 83 MHz Maximum Clock Cycle Time Self Timed Write Separate Data Input and Data Output Pins Pass- Through Feature Asynchronous Output Enable (G) LVTTL patible I/O No Dead Cycles Required for Reads after Writes or for Writes after Reads 100 Pin TQFP Package Simultaneous Reads and Writes - Routers -...