The MC92305 is interfaced to a single 8-bit (10-bit for
256 QAM) A/D converter which is clocked at 4 times the
symbol rate (4Rs). A pin-programmable input format se-
lector allows the use of A/D converters which produce out-
put samples in either offset binary or 2's complement
The demodulator function performs all required sig-
nal processing to extract the I and Q symbols from the re-
ceived data stream. Fully internal digital clock recovery/
synchronization, Nyquist filtering and LTE/DFE adaptive
equalization are employed to recover symbol information
in the presence of channel noise and micro-reflections.
The equalizer is able to converge with random received
data and no special training sequence is required.
Single-bit (Sigma-Delta converted) outputs are pro-
vided for automatic gain control (AGC) and A/D voltage
controlled oscillator(VCO) feedback functions within the
external IF circuitry.
After synchronization with the MPEG framing struc-
ture the data stream is convolutionally de-interleaved. To
obtain the maximum data throughput (i.e. minimum la-
tency) under various channel SNR's the de-interleaver
can be programmed.
Table 1 describes the usable parameter settings
with varying delay (latency) and burst (error correction).
N is the block size in bytes, DEPTH is the number of
paths in the de-interleaver and INC is the increment (in
bytes) in which data is moved through the de-interleaver
paths. DELAY is defined as the latency (in bytes) in the
de-interleaver (after frame synchronization has been
achieved) and BURST is defined as the maximum num-
ber of bytes that can be affected by bursty noise before
more than eight bytes are corrupted in a de-interleaved
MPEG frame. Minimum burst error correction of 8 bytes
is guaranteed by the Reed Solomon decoder.
Table 1. De-Interleaver Conﬁgurations
The demodulator carrier tracking loop is capable of
locking to signals which contain moderate frequency off-
sets (0.06Rs) from the specified IF frequencies. The car-
rier tracking loop is normally closed digitally, using an
internal numerically controlled oscillator (NCO) but a sin-
gle bit control output is also provided for closing the loop
through an external VCO.
External signals indicate when the demodulator has
successfully acquired the data stream and recovered the
data clock (MSSLOCK), and when the received symbols
are consistently below a programmable error threshold
Symbol To Byte Mapping
The received symbols are mapped into bytes accord-
ing to the DVB/Davic 1.0 specifications. An internal I2C
register can be used to select an alternative de-coding
scheme which is specified as a mask programmable op-
Sync Word Synchronization.
After demodulation of the received data, the byte
stream is examined for MPEG synchronization (inverted
and non-inverted) bytes and when the number detected
exceeds programmable thresholds, the received byte
stream is recognized as valid MPEG data.
FRAME_SYNCH is asserted when the programmed num-
ber of synchronization bytes have been recognized.
FRAME_START is asserted for one byte width at the start
of each MPEG frame.
The operation of the de-interleaver is software con-
figurable via the I2C interface during system operation.
Reed Solomon Decoding
The Reed Solomon decoder block implements a
shortened Reed-Solomon decoder with field generator
polynomial X8 + X4 + X3 + X2 + 1 as per the DVB speci-
The decoder is able to correct up to 8 byte errors in
each received packet. Following error correction the
Reed Solomon decoder outputs the MPEG packets and
asserts the DO_VAL output for each byte output (50%
duty cycle per byte).
If the error correcting ability of the Reed Solomon
decoder is exceeded (more than 8 byte errors in a single
packet), the original, uncorrected, data is output and the
DO_VAL output is not asserted. The FRAME_ERR sig-
nal is asserted for the duration of the uncorrected MPEG