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Motorola Electronic Components Datasheet

MC88921DW Datasheet

LOW SKEW CMOS PLL CLOCK DRIVER With Power-Down/ Power-Up Feature

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MC88921DW pdf
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Order this document
from Logic Marketing
Low Skew CMOS PLL
Clock Driver
With Power-Down/Power-Up Feature
MC88921
The MC88921 Clock Driver utilizes phase–locked loop technology to
lock its low skew outputs’ frequency and phase onto an input reference
clock. It is designed to provide clock distribution for CISC microprocessor
or single processor RISC systems.
The PLL allows the high current, low skew outputs to lock onto a single
clock input and distribute it with essentially zero delay to multiple
locations on a board. The PLL also allows the MC88921 to multiply a low
frequency input clock and distribute it locally at a higher (2X) system
frequency.
LOW SKEW CMOS PLL
CLOCK DRIVER
With Power–Down/
Power–Up Feature
2X_Q Output Meets All Requirements of the 20, 25 and 33MHz 68040
Microprocessor PCLK Input Specifications
60 and 66MHz Output to Drive the PentiumMicroprocessor
Four Outputs (Q0–Q3) With Output–Output Skew <500ps and Six
Outputs Total (Q0–Q3, 2X_Q) With <1ns Skew Each Being Phase and
Frequency Locked to the SYNC Input
The Phase Variation From Part–to–Part Between SYNC and the ‘Q’
Outputs Is Less Than 600ps (Derived From the TPD Specification,
Which Defines the Part–to–Part Skew)
SYNC Input Frequency Range From 5MHZ to 2X_Q FMax/4
Additional Outputs Available at 2X the System ‘Q’ Frequency
All Outputs Have ±36mA Drive (Equal High and Low) CMOS Levels.
Can Drive Either CMOS or TTL Inputs. All Inputs Are TTL–Level
Compatible
Test Mode Pin (PLL_EN) Provided for Low Frequency Testing
Special Power–Down Mode With 2X_Q, Q0, and Q1 Being Reset (With
MR), and Other Outputs Remain Running. 2X_Q, Q0 and Q1 Are
Guaranteed to Be in Lock 3 Clock Cycles After MR Is Negated
20
1
DW SUFFIX
SOIC PACKAGE
CASE 751D–04
Four ‘Q’ outputs (Q0–Q3) are provided with less than 500ps skew between their rising edges. A 2X_Q output runs at twice the
‘Q’ output frequency. The 2X_Q output is ideal for 68040 systems which require a 2X processor clock input. The 2X_Q output
meets the tight duty cycle spec of the 20, 25 and 33MHz 68040. The 66MHz 2X_Q output can also be used for driving the clock
input of the Pentium Microprocessor while providing multiple 33MHz outputs to drive the support and bus logic. The FBSEL pin
allows the user to internally feedback either the Q or the Q/2 frequency providing a 1x or 2x multiplication factor of the reference
input.
In normal phase–locked operation the PLL_EN pin is held high. Pulling the PLL_EN pin low disables the VCO and puts the
88921 in a static ‘test mode’. In this mode there is no frequency limitation on the input clock, which is necessary for a low
frequency board test environment.
A lock indicator output (LOCK) will go HIGH when the loop is in steady state phase and frequency lock. The output will go LOW
if phase–lock is lost or when the PLL_EN pin is LOW. The lock output will go HIGH no later than 10ms after the 88921 sees a sync
signal and full 5.0V VCC.
Pentium is a trademark of the Intel Corporation.
8/95
© Motorola, Inc. 1995
1
REV 2


Motorola Electronic Components Datasheet

MC88921DW Datasheet

LOW SKEW CMOS PLL CLOCK DRIVER With Power-Down/ Power-Up Feature

No Preview Available !

MC88921DW pdf
MC88921
Power–Down Mode Functionality
The MC88921 has a special feature
designed in to allow the processor clock
inputs to be reset for total processor
power–down, and then to return to
phase–locked operation very quickly when
the processor is powered–up again.
The MR pin resets outputs 2X_Q, Q0
and Q1 only leaving the other outputs
operational for other system activity. When
MR is negated, all outputs will be operating
normally within 3 clock cycles.
CAPACITANCE AND POWER SPECIFICATIONS
Symbol
Parameter
CIN
CPD
PD1
PD2
Input Capacitance
Power Dissipation Capacitance
Power Dissipation at 33MHz With 50
Thevenin Termination
Power Dissipation at 33MHz With 50
Parallel Termination to GND
Q3 1
VCC 2
MR 3
PLL_EN 4
VCC(AN) 5
RC1 6
GND(AN) 7
SYNC 8
GND 9
Q0 10
20 GND
19 2X_Q
18 Q/2
17 VCC
16 Q2
15 GND
14 LOCK
13 FBSEL
12 Q1
11 VCC
Pinout: 20–Lead Wide SOIC Package (Top View)
Value Typ
4.5
40
15mW/Output
90mW/Device
37.5mW/Output
225mW/Device
Unit
pF
pF
mW
mW
Test Conditions
VCC = 5.0V
VCC = 5.0V
VCC = 5.0V
T = 25°C
VCC = 5.0V
T = 25°C
MAXIMUM RATINGS*
Symbol
Parameter
Limits
Unit
VCC, AVCC
Vin
Vout
Iin
Iout
ICC
Tstg
DC Supply Voltage Referenced to GND
DC Input Voltage (Referenced to GND)
DC Output Voltage (Referenced to GND)
DC Input Current, Per Pin
DC Output Sink/Source Current, Per Pin
DC VCC or GND Current Per Output Pin
Storage Temperature
–0.5 to 7.0
–0.5 to VCC +0.5
–0.5 to VCC +0.5
±20
±50
±50
–65 to +150
V
V
V
mA
mA
mA
°C
* Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the
Recommended Operating Conditions.
MOTOROLA
2 TIMING SOLUTIONS
BR1333 — REV 5


Part Number MC88921DW
Description LOW SKEW CMOS PLL CLOCK DRIVER With Power-Down/ Power-Up Feature
Maker Motorola
Total Page 10 Pages
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