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Motorola Electronic Components Datasheet

MC54HC259A Datasheet

8-Bit Addressable Latch 1-of-8 Decoder

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MC54HC259A pdf
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Product Preview
8-Bit Addressable Latch
1-of-8 Decoder
High–Performance Silicon–Gate CMOS
The MC54/74HC259A is identical in pinout to the LS259. The device
inputs are compatible with standard CMOS outputs; with pullup resistors,
they are compatible with LSTTL outputs.
The HC259A has four modes of operation as shown in the mode selection
table. In the addressable latch mode, the data on Data In is written into the
addressed latch. The addressed latch follows the data input with all
non–addressed latches remaining in their previous states. In the memory
mode, all latches remain in their previous state and are unaffected by the
Data or Address inputs. In the one–of–eight decoding or demultiplexing
mode, the addressed output follows the state of Data In with all other outputs
in the LOW state. In the Reset mode all outputs are LOW and unaffected by
the address and data inputs. When operating the HC259A as an
addressable latch, changing more than one bit of the address could impose
a transient wrong address. Therefore, this should only be done while in the
memory mode.
Output Drive Capability: 10 LSTTL Loads
Outputs Directly Interface to CMOS, NMOS, and TTL
Operating Voltage Range: 2 to 6 V
Low Input Current: 1 µA
High Noise Immunity Characteristic of CMOS Devices
In Compliance with the Requirements Defined by JEDEC Standard
No. 7A
Chip Complexity: 202 FETs or 50.5 Equivalent Gates
LOGIC DIAGRAM
ADDRESS
INPUTS
A0 1
A1 2
A2 3
DATA IN 13
RESET 15
ENABLE 14
4 Q0
5 Q1
6 Q2
7 Q3
9 Q4
10 Q5
11 Q6
12 Q7
NONINVERTING
OUTPUTS
PIN 16 = VCC
PIN 8 = GND
MC54/74HC259A
16
1
J SUFFIX
CERAMIC PACKAGE
CASE 620–10
16
1
16
1
16
1
N SUFFIX
PLASTIC PACKAGE
CASE 648–08
D SUFFIX
SOIC PACKAGE
CASE 751B–05
DT SUFFIX
TSSOP PACKAGE
CASE 948F–01
ORDERING INFORMATION
MC54HCXXXAJ
MC74HCXXXAN
MC74HCXXXAD
MC74HCXXXADT
Ceramic
Plastic
SOIC
TSSOP
PIN ASSIGNMENT
A0 1
A1 2
16 VCC
15 RESET
A2 3
14 ENABLE
Q0 4
Q1 5
13 DATA IN
12 Q7
Q2 6
Q3 7
GND 8
11 Q6
10 Q5
9 Q4
MODE SELECTION TABLE
Enable
L
H
L
H
Reset
H
H
L
L
Mode
Addressable Latch
Memory
8–Line Demultiplexer
Reset
LATCH SELECTION TABLE
Address Inputs
CBA
Latch
Addressed
LLL
L LH
LHL
L HH
HL L
HLH
HH L
HHH
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
This document contains information on a product under development. Motorola reserves the right to change or discontinue this product without notice.
10/95
© Motorola, Inc. 1995
1 REV 0


Motorola Electronic Components Datasheet

MC54HC259A Datasheet

8-Bit Addressable Latch 1-of-8 Decoder

No Preview Available !

MC54HC259A pdf
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎMC54/74HC259A
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎMAXIMUM RATINGS*
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎSymbol
Parameter
Value
Unit
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎVCC
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎVin
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎVout
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎIin
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎIout
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎICC
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎPD
DC Supply Voltage (Referenced to GND)
– 0.5 to + 7.0
V
DC Input Voltage (Referenced to GND)
DC Output Voltage (Referenced to GND)
DC Input Current, per Pin
– 0.5 to VCC + 0.5
– 0.5 to VCC + 0.5
± 20
V
V
mA
DC Output Current, per Pin
± 25 mA
DC Supply Current, VCC and GND Pins
Power Dissipation in Still Air, Plastic or Ceramic DIP†
SOIC Package†
TSSOP Package†
± 50
750
500
450
mA
mW
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎTstg Storage Temperature
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎTL Lead Temperature, 1 mm from Case for 10 Seconds
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎPlastic DIP, SOIC or TSSOP Package
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ(Ceramic DIP)
– 65 to + 150
260
300
_C
_C
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ* Maximum Ratings are those values beyond which damage to the device may occur.
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high–impedance cir-
cuit. For proper operation, Vin and
v vVout should be constrained to the
range GND (Vin or Vout) VCC.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or VCC).
Unused outputs must be left open.
Functional operation should be restricted to the Recommended Operating Conditions.
†Derating — Plastic DIP: – 10 mW/_C from 65_ to 125_C
Ceramic DIP: – 10 mW/_C from 100_ to 125_C
SOIC Package: – 7 mW/_C from 65_ to 125_C
TSSOP Package: – 6.1 mW/_C from 65_ to 125_C
For high frequency or heavy load considerations, see Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎRECOMMENDED OPERATING CONDITIONS
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎSymbol
Parameter
Min Max Unit
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎVCC
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎVin, Vout
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎTA
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎtr, tf
DC Supply Voltage (Referenced to GND)
DC Input Voltage, Output Voltage (Referenced to GND)
Operating Temperature, All Package Types
Input Rise and Fall Time
(Figure 1)
VCC = 2.0 V
VCC = 3.0 V
VCC = 4.5 V
VCC = 6.0 V
2.0
0
– 55
0
0
0
0
6.0
VCC
+ 125
1000
600
500
400
V
V
_C
ns
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎDC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎSymbol
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎVIH
Parameter
Minimum High–Level Input
Voltage
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎVIL MaximumLow–LevelInput
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎVoltage
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎVOH
Minimum High–Level Output
Voltage
Test Conditions
vVout = 0.1 V or VCC – 0.1 V
|Iout| 20 µA
vVout = 0.1 V or VCC – 0.1 V
|Iout| 20 µA
vVin = VIH or VIL
|Iout| 20 µA
vVin = VIH or VIL |Iout|
v|Iout|
v|Iout|
2.4 mA
4.0 mA
5.2 mA
VCC
V
2.0
3.0
4.5
6.0
2.0
3.0
4.5
6.0
2.0
4.5
6.0
3.0
4.5
6.0
Guaranteed Limit
v v– 55 to
25_C
85_C
125_C
1.5 1.5 1.5
2.1 2.1 2.1
3.15 3.15 3.15
4.2 4.2 4.2
0.5 0.5 0.5
0.9 0.9 0.9
1.35 1.35 1.35
1.80 1.80 1.80
1.9 1.9 1.9
4.4 4.4 4.4
5.9 5.9 5.9
2.48 2.34 2.20
3.98 3.84 3.70
5.48 5.34 5.20
Unit
V
V
V
MOTOROLA
2 High–Speed CMOS Logic Data
DL129 — Rev 6


Part Number MC54HC259A
Description 8-Bit Addressable Latch 1-of-8 Decoder
Maker Motorola
Total Page 8 Pages
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