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Motorola Electronic Components Datasheet

MC54F373 Datasheet

OCTAL TRANSPARENT LATCH

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MC54F373 pdf
OCTAL TRANSPARENT LATCH
WITH 3-STATE OUTPUTS
The MC54/74F373 consists of eight latches with 3-state outputs for bus or-
ganized system applications. The flip-flops appear transparent to the data
when Latch Enable (LE) is HIGH. When LE is LOW, the data that meets the
setup times is latched. Data appears on the bus when the Output Enable (OE)
is LOW. When OE is HIGH the bus output is in the high impedance state.
Eight Latches in a Single Package
3-State Outputs for Bus Interfacing
ESD > 4000 Volts
CONNECTION DIAGRAM (TOP VIEW)
VCC O7 D7 D6 O6 O5 D5 D4 O4
20 19 18 17 16 15 14 13 12
LE
11
MC54/74F373
OCTAL TRANSPARENT LATCH
WITH 3-STATE OUTPUTS
FASTSCHOTTKY TTL
20
1
J SUFFIX
CERAMIC
CASE 732-03
1 2 3 4 5 6 7 8 9 10
OE O0 D0 D1 O1 O2 D2 D3 O3 GND
LOGIC SYMBOL
3 4 7 8 13 14 17 18
D0 D1 D2 D3 D4 D5 D6 D7
11 LE
1 OE
O0 O1 O2 O3 O4 O5 O6 O7
VCC = PIN 20
GND = PIN 10
2 5 6 9 12 15 16 19
20
1
N SUFFIX
PLASTIC
CASE 738-03
20
1
DW SUFFIX
SOIC
CASE 751D-03
ORDERING INFORMATION
MC54FXXXJ Ceramic
MC74FXXXN Plastic
MC74FXXXDW SOIC
GUARANTEED OPERATING RANGES
Symbol
Parameter
VCC
TA
Supply Voltage
Operating Ambient Temperature Range
IOH Output Current — HIGH
IOL Output Current — LOW
Min Typ Max Unit
54, 74
4.5
5.0
5.5
V
54 –55 25 125 °C
74 0 25 70
54, 74
–3.0 mA
54, 74
24 mA
FAST AND LS TTL DATA
4-167


Motorola Electronic Components Datasheet

MC54F373 Datasheet

OCTAL TRANSPARENT LATCH

No Preview Available !

MC54F373 pdf
MC54/74F373
FUNCTIONAL DESCRIPTION
The F373 contains eight D-type latches with 3-state output
buffers. When the Latch Enable (LE) input is HIGH, data on the
Dn inputs enters the latches. In this condition the latches are
transparent; i.e., a latch output will change state each time its
D input changes. When LE is LOW the latches store the
information that was present on the D inputs one setup time
preceding the HIGH-to-LOW transition of LE. The 3-state buff-
ers are controlled by the Output Enable (OE) input. When (OE)
is LOW, the buffers are in the bi-state mode. When OE is HIGH
the buffers are in the high impedance mode, but this does not
interfere with entering new data into the latches.
LOGIC DIAGRAM
D0 D1 D2 D3 D4 D5 D6 D7
DD DDDD DD
GO GO GO GO GO GO GO GO
LE
OE
O0 O1 O2 O3 O4 O5 O6 O7
NOTE:
This diagram is provided only for the understanding of logic
operations and should not be used to estimate propagation delays.
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
Limits
Symbol
Parameter
Min Typ Max Unit
Test Conditions
VIH Input HIGH Voltage
2.0 V Guaranteed Input HIGH Voltage
VIL Input LOW Voltage
0.8 V Guaranteed Input LOW Voltage
VIK Input Clamp Diode Voltage
–1.2 V IIN = –18 mA
VCC = MIN
VOH
Output HIGH Voltage
54, 74 2.4
3.3
V IOH = – 3.0 mA
VCC = 4.5 V
74 2.7 3.3
V IOH = – 3.0 mA
VCC = 4.75 V
VOL
Output LOW Voltage
0.35 0.5
V IOL = 24 mA
VCC = MIN
IOZH
Output OFF Current — HIGH
50 µA VOUT = 2.7 V
VCC = MAX
IOZL
Output OFF Current — LOW
–50 µA VOUT = 0.5 V
VCC = MAX
IIH Input HIGH Current
20 µA VIN = 2.7 V
VCC = MAX
100 µA VIN = 7.0 V
VCC = MAX
IIL Input LOW Current
–0.6 mA VIN = 0.5 V
VCC = MAX
IOS Output Short Circuit Current (Note 2) –60
–150 mA VOUT = 0 V
VCC = MAX
ICCZ
Power Supply Current (All Outputs OFF)
35 55 mA OE = 4.5 V
Dn, LE = GND
VCC = MAX
NOTES:
1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable device type.
2. Not more than one output should be shorted at a time, nor for more than 1 second.
FAST AND LS TTL DATA
4-168


Part Number MC54F373
Description OCTAL TRANSPARENT LATCH
Maker Motorola
Total Page 3 Pages
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