| Description | Pin Name PD0-7 PXCK SA SCL SDA FC0-2 REFSQ SCSYNC PALID COMPSYNC CLAMP Pin No. 2-4, 38-42 44 18 23 24 12-14 9 8 7 6 5 Description 8 Bit Pixel Data inputs clocked by PXCK. PD0 is the least significant bit. These pins are internally pulled low. 27MHz Pixel Clock input. The VP5313/VP5513 internally divides PXCK by two to provide the pixel clock. Slave address select. Standard I2C bus serial clock in... |
| Features |
9 s Converts Y, Cr, Cb data to analog RGB and composite 10 or S-video and composite video 11 s Supports CCIR recommendations 601 and 656 12 s All digital video encoding 13 s Selectable master/slave mode for sync signals 14 s Switchable chrominance bandwidth s CCIR 624 PAL SMPTE or 170M NTSC compatible 15 outputs 16 s GENLOCK mode 17 s I2C bus seria...
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| Datasheet |
 VP5313 Datasheet - 151.79KB |
