Using a PIC16C5X as a Smart I2C™ Peripheral
NII Norsat International Inc.
PIC16C5X microcontrollers from Microchip are ideally
suited for use as smart peripheral devices under the con-
trol of the main processors in systems, due to their low
cost and high speed. They are capable of performing
tasks which would simply overload a conventional micro-
processor, or require considerable logic circuitry, at a
cost competitive with lower mid-range PLDs.To minimize
the engineering overhead of adding multiple controllers
to a product, it is convenient for the auxiliary controllers
to emulate standard I/O peripherals.
A common interface found in existing products is the I2C
bus. This efﬁcient, two-wire, bi-directional interface
allows the designer to connect multiple devices together,
with the microprocessor able to send data to and receive
data from any device on the bus. This interface is found
on a variety of components, such as PLLs, DACs, video
controllers, and EEPROMs. If a product already contains
one or more I2C devices, it is simple to add a PIC16C5X
emulating a compatible component.
This application note describes the implementation of a
standard slave device with multiple, bi-directional
registers. A subset of the full I2C speciﬁcation is
supported, which can be controlled by the same
software which would talk to a Microchip 24LCXX
THE I2C BUS
The I2C bus is a master-slave two-wire interface,
consisting of a clock line (SCL) and a data line (SDA).
Bi-directional communication (and in a full,
multi-master system, collision detection, and clock
synchronization) is facilitated through the use of a
“wire-and” (i.e., active-low, passive-high) connection.
The standard mode I2C bus supports SCL clock
frequencies up to 100 kHz. The fast-mode I2C bus sup-
ports clock rates up to 400 kHz. This application note will
support the 100 kHz (standard-mode) clock rate.
Each device has a unique seven bit address, which the
master uses to access each individual slave device.
During normal communication, the SDA line is only per-
mitted to change while the SCL line is low, thus providing
two violation conditions (Figure 1) which are used to sig-
nal a start condition (SDA drops while SCL is high) and a
stop condition (SDA rises while SCL is high), which frame
FIGURE 1: I2C TIMING
tSH tCL tCH
1 1 0 1 1 1 1 R/W A
Each byte of a transfer is 9-bits long (see timing chart
in the program listing). The talker sends 8 data bits
followed by a '1' bit. The listener acknowledges the
receipt of the byte and gives permission to send the
next byte by inserting a '0' bit over the trailing '1'. The lis-
tener may indicate "not ready for data" by leaving the
acknowledge bit as a '1'.
The clock is generated by the master only. The slave
device must respond to the master within the timing
speciﬁcations of the I2C deﬁnition otherwise the master
would be required to operate in slow mode, which most
software implementations of I2C masters do not
actually support. The speciﬁed (standard-mode) tCL is
4.7 µs, and tCH is only 4 µs, so it would be extremely dif-
ﬁcult to achieve the timing of a hardware slave device
with a conventional microcontroller.
A message is always initiated by the master, and begins
with a start condition, followed by a slave address
(7 MSbs) and direction bit (LSb = '1' for READ, '0' for
WRITE). The addressed slave must acknowledge this
byte if it is ready to communicate any data. If the slave
fails to respond, the master should initiate a stop condi-
tion and retry.
If the direction bit is '0' the next byte is considered the
sub-address (this is an extension to I2C used by most
multi-register devices). The sub-address selects which
"register" or “function” subsequent read or write
operations will affect. Any additional bytes will be received
and stored in consecutive locations until a stop is sent. If
the slave is unable to process more data, it could termi-
nate transfer by not acknowledging the last byte.
© 1997 Microchip Technology Inc.