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  Microchip Technology Semiconductor Electronic Components Datasheet  

AN541 Datasheet

Using PIC16C5x as a Smart IIC Peripheral

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AN541
Using a PIC16C5X as a Smart I2CPeripheral
Author:
Don Lekei
NII Norsat International Inc.
INTRODUCTION
PIC16C5X microcontrollers from Microchip are ideally
suited for use as smart peripheral devices under the con-
trol of the main processors in systems, due to their low
cost and high speed. They are capable of performing
tasks which would simply overload a conventional micro-
processor, or require considerable logic circuitry, at a
cost competitive with lower mid-range PLDs.To minimize
the engineering overhead of adding multiple controllers
to a product, it is convenient for the auxiliary controllers
to emulate standard I/O peripherals.
A common interface found in existing products is the I2C
bus. This efficient, two-wire, bi-directional interface
allows the designer to connect multiple devices together,
with the microprocessor able to send data to and receive
data from any device on the bus. This interface is found
on a variety of components, such as PLLs, DACs, video
controllers, and EEPROMs. If a product already contains
one or more I2C devices, it is simple to add a PIC16C5X
emulating a compatible component.
This application note describes the implementation of a
standard slave device with multiple, bi-directional
registers. A subset of the full I2C specification is
supported, which can be controlled by the same
software which would talk to a Microchip 24LCXX
series EEPROM.
THE I2C BUS
The I2C bus is a master-slave two-wire interface,
consisting of a clock line (SCL) and a data line (SDA).
Bi-directional communication (and in a full,
multi-master system, collision detection, and clock
synchronization) is facilitated through the use of a
“wire-and” (i.e., active-low, passive-high) connection.
The standard mode I2C bus supports SCL clock
frequencies up to 100 kHz. The fast-mode I2C bus sup-
ports clock rates up to 400 kHz. This application note will
support the 100 kHz (standard-mode) clock rate.
Each device has a unique seven bit address, which the
master uses to access each individual slave device.
During normal communication, the SDA line is only per-
mitted to change while the SCL line is low, thus providing
two violation conditions (Figure 1) which are used to sig-
nal a start condition (SDA drops while SCL is high) and a
stop condition (SDA rises while SCL is high), which frame
a message.
FIGURE 1: I2C TIMING
SCL
SDA
tSH tCL tCH
Start
Data Bit
More Bits
Stop
SDA
SCL
1 1 0 1 1 1 1 R/W A
Each byte of a transfer is 9-bits long (see timing chart
in the program listing). The talker sends 8 data bits
followed by a '1' bit. The listener acknowledges the
receipt of the byte and gives permission to send the
next byte by inserting a '0' bit over the trailing '1'. The lis-
tener may indicate "not ready for data" by leaving the
acknowledge bit as a '1'.
The clock is generated by the master only. The slave
device must respond to the master within the timing
specifications of the I2C definition otherwise the master
would be required to operate in slow mode, which most
software implementations of I2C masters do not
actually support. The specified (standard-mode) tCL is
4.7 µs, and tCH is only 4 µs, so it would be extremely dif-
ficult to achieve the timing of a hardware slave device
with a conventional microcontroller.
MESSAGE FORMAT
A message is always initiated by the master, and begins
with a start condition, followed by a slave address
(7 MSbs) and direction bit (LSb = '1' for READ, '0' for
WRITE). The addressed slave must acknowledge this
byte if it is ready to communicate any data. If the slave
fails to respond, the master should initiate a stop condi-
tion and retry.
If the direction bit is '0' the next byte is considered the
sub-address (this is an extension to I2C used by most
multi-register devices). The sub-address selects which
"register" or “function” subsequent read or write
operations will affect. Any additional bytes will be received
and stored in consecutive locations until a stop is sent. If
the slave is unable to process more data, it could termi-
nate transfer by not acknowledging the last byte.
© 1997 Microchip Technology Inc.
DS00541E-page 1


  Microchip Technology Semiconductor Electronic Components Datasheet  

AN541 Datasheet

Using PIC16C5x as a Smart IIC Peripheral

No Preview Available !

AN541 pdf
AN541
If the direction bit is '1', the slave will transfer successive
bytes to the master (the master holds the line at '1'),
wwwwh.iDleathaSehmeeats4tUe.rcoamcknowledges each byte with a '0' in
the ninth bit. The master can terminate the transfer by
not acknowledging the last byte, while the slave can
stop the transfer by generating a stop condition.
The start address of a read operation is set by sending
a write request with a sub-address only (no data bytes).
For a detailed set of timing diagrams and different
communication modes, consult any of the Microchip
24LCXX EEPROM specifications. This program
communicates using the same formats.
IMPLEMENTATION
The chip will respond to slave address
"DEVICE_ADDRESS", which by default is D616 (D716
for read). This address was chosen because it is the
fourth optional address of a Philips PCF8573
clock /calender or a TDA8443 tipple video switch
(unlikely that a product would contain four of those).
FIGURE 2: SCHEMATIC OF I2C
CONNECTIONS
+5V
R2*
SDA
SCL
+5V U1
1
2
RA2
3 RA3
4 T0CKI
5 MCLR
6 VSS
7 RB0
8
9
RB1
RB2
RB3
RA1
RA0
OSC1
OSC2
VDD
RB7
RB6
RB5
RB4
18
17
16
15
14
13
12
11
10
PIC16C5X
100
X1
20 MHz
*R2 may be needed if not
provided at the master.
15 pF
15 pF
The connections to the device are shown in Figure 2.
The use of RA0 for data input is required. Data is
shifted directly out of the port. The code could be mod-
ified to make it port independent, but the loss of effi-
ciency may hinder some real-time applications.
This application emulates an I2C device with
8 registers, accessed as sub-addresses 1 through 8
(module 7), plus a data channel (0). The example code
returns an ID string when the data channel is accessed.
When bytes are written to sub-addresses other than 0,
they are stored in I2CR0-I2CR7 (I2CR0 gets data
written to sub-address 8).
FIGURE 3: I2C DEVICE FLOWCHART
Reset
Initialize I2C Ports
Reset I2C Places
Do Main User Task
No SDA and
SCL both High?
Yes
Do Main User Task
X, 0 Test 1, 1
SCL, SDA
1, 0
Clock in 8-bits
Stop
No Slave
address correct?
Yes
Send ACK
Stop
Bit = 0?
Yes
Clock in 8-bits
No
Send ACK
Get sub-address
Clock out 8-bits
Send ACK
Process Byte
Stop?
Yes No
Stop?
No
Clock in 8-bits
Send ACK
Yes
User Message
Cleanup Code
Get Sub-Address
Process Message
DS00541E-page 2
© 1997 Microchip Technology Inc.


Part Number AN541
Description Using PIC16C5x as a Smart IIC Peripheral
Maker Microchip Technology
Total Page 16 Pages
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