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  Microchip Technology Semiconductor Electronic Components Datasheet  

MCP19117 Datasheet

Digitally Enhanced Power Analog Synchronous Low-Side PWM Controller

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MCP19117 pdf
MCP19116/7
Digitally Enhanced Power Analog Synchronous Low-Side PWM Controller
with Improved 8k Word Core
Features
• Input Voltage: +4.5V to +42V
• Can be configured with multiple topologies includ-
ing but not limited to:
- Flyback
- Ćuk
- Boost
- SEPIC (Single-Ended Primary-Inductor
Converter)
• Capable of Quasi-Resonant or Fixed-Frequency
Operation
• Low Quiescent Current: 5 mA Typical
• Low Sleep Current: 50 µA Typical
• Low-Side Gate Drivers:
- +5V gate drive with 0.5A sink/source current
- +10V gate drive with 1A sink/source current
• Peak Current Mode Control
• Differential Remote Output Sense
• Multiple Output Systems:
- Master or Slave
• AEC-Q100 Qualified
• Configurable Parameters:
- VREF, Precision IOUT/VOUT Set Point (DAC)
- ADC Reference Switch (VDD or AVDD)
- Input Undervoltage Lockout (UVLO)
- Input Overvoltage Lockout (OVLO)
- Detection and protection
- Primary current leading edge blanking (0 ns,
50 ns, 100 ns and 200 ns)
- Gate drive dead time (16 ns to 256 ns)
- Fixed switching frequency range:
31.25 kHz to 2.0 MHz
- Slope compensation
- Quasi-Resonant configuration with built-in
comparator and programmable offset voltage
adjustment
- Primary current offset adjustment
- GPIO pin options
• Integrated Low-Side Differential Current-Sense
Amplifier
• Better than 5% Current Regulation
• Thermal Shutdown
Microcontroller Features
• Precision 8 MHz Internal Oscillator Block:
- Factory-calibrated to ±1%, typical
• Interrupt-Capable:
- Firmware
- Interrupt-on-change pins
• Only 35 Instructions to Learn
• 8192 Words On-Chip Program Memory
• High-Endurance Flash:
- 100,000 write Flash endurance
- Flash retention: > 40 years
• Watchdog Timer (WDT) with Independent
Oscillator for Reliable Operation
• Programmable Code Protection
• In-Circuit Serial Programming™ (ICSP™) via Two
Pins
• Eight I/O Pins and One Input-Only Pin:
- Two open-drain pins
• Analog-to-Digital Converter (ADC):
- 10-bit resolution
- Five external channels
• Timer0: 8-bit Timer/Counter with 8-bit Prescaler
• Enhanced Timer1:
- 16-bit timer with prescaler
- Two selectable clock sources
• Timer2: 8-Bit Timer with Prescaler:
- 8-bit period register
• I2C Communication:
- 7-bit address masking
- Two dedicated address registers
• Addressable Universal Synchronous Receiver
Transmitter (AUSART) Modes
- Asynchronous (Full Duplex)
- Synchronous - Master (Half Duplex)
- Synchronous - Slave (Half Duplex)
2015-2016 Microchip Technology Inc.
DS20005479B-page 1



  Microchip Technology Semiconductor Electronic Components Datasheet  

MCP19117 Datasheet

Digitally Enhanced Power Analog Synchronous Low-Side PWM Controller

No Preview Available !

MCP19117 pdf
MCP19116/7
Pin Diagram – 24-Pin QFN (MCP19116)
24 23 22 21 20
GPA0/AN0/TEST_OUT 1
GPA1/AN1/CLKPIN 2
GPA2/AN2/T0CKI/INT 3
GPA3/AN3 4
MCP19116
GPA7/SCL/ICSPCLK 5
GPA6/CCD/ICSPDAT/RX/DT 6
7
EXP-25
89
10 11
19
18 VDR
17 PDRV
16 SDRV
15 PGND
14 AGND
13 IP
12
DS20005479B-page 2
2015-2016 Microchip Technology Inc.



  Microchip Technology Semiconductor Electronic Components Datasheet  

MCP19117 Datasheet

Digitally Enhanced Power Analog Synchronous Low-Side PWM Controller

No Preview Available !

MCP19117 pdf
MCP19116/7
TABLE 1: 24-PIN QFN (MCP19116) SUMMARY
Basic
Additional
GPA0
1 Y AN0
— IOC Y
Analog/Digital Debug Output (1)
GPA1
2 Y AN1
— IOC Y
Sync Signal In/Out (2)
GPA2
3 Y AN2 T0CKI —
IOC
Y
INT
——
GPA3
4 Y AN3
— IOC Y
——
GPA5
7N
IOC (3) Y (4)
MCLR Test Enable Input
GPA6
6N
— RX/DT IOC
Y ICSPDAT Dual Capture / Single Compare1
Input
GPA7
5N
— SCL IOC N ICSPCLK —
GPB0 8 N
— SDA IOC N
——
GPB1 24 Y AN4
— TX/CK IOC
Y
— VREF2 (5)
DESATN 9 N
DESATP/ 10 N
ISOUT
— DESAT Negative Input
— DESATP Input or ISOUT
Output (6)
ISP
11 N
Y
— Current Sense Amplifier Positive
Input
ISN
12 N
— Current Sense Amplifier
Negative Input
IP
13 N
— Primary Input Current Sense
AGND
14 N
AGND Small Signal Ground
PGND
15 N
PGND Large Signal Ground
SDRV 16 N
— Secondary LS Gate Drive
Output
PDRV 17 N
— Primary LS Gate Drive
Output
VDR
VDD
VIN
VS
IFB
ICOMP
Note 1:
18 N
19 N
20 N
21 N
VDR Gate Drive Supply Voltage
VDD VDD Output
VIN Input Supply Voltage
— Output Voltage Sense
22 N
— Error Amplifier Feedback Input
23 N
— Error Amplifier Output
The Analog/Digital Debug Output is selected through the control of the ABECON register.
2: Selected when functioning as master or slave by proper configuration of the MSC<1:0> bits in the
MODECON register.
3: The IOC is disabled when MCLR is enabled.
4: Weak pull-up always enabled when MCLR is enabled, otherwise the pull-up is under user control.
5: VREF2 output selected when configured as master by proper configuration of the MSC<1:0> bits in the
MODECON register.
6: When RFB of MODECON<5> = 0, the internal feedback resistor and DESATP input are enabled. When
RFB = 1, ISOUT is enabled.
2015-2016 Microchip Technology Inc.
DS20005479B-page 3




Part Number MCP19117
Description Digitally Enhanced Power Analog Synchronous Low-Side PWM Controller
Maker Microchip
Total Page 30 Pages
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