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Maxim Integrated Semiconductor Electronic Components Datasheet

MAX1002 Datasheet

Low-Power / 60Msps / Dual / 6-Bit ADC

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MAX1002 pdf
19-1270; Rev 0; 7/97
EVAALVUAAILTAIOBNLEKIT
Low-Power, 60Msps, Dual, 6-Bit ADC
_______________General Description
The MAX1002 is a dual, 6-bit analog-to-digital converter
(ADC) that combines high-speed, low-power operation
with a user-selectable input range, an internal refer-
ence, and a clock oscillator. The dual, parallel ADCs
are designed to convert in-phase (I) and quadrature
(Q) analog signals into two 6-bit offset-binary-coded
digital outputs at sampling rates up to 60Msps while
achieving typical integral nonlinearity (INL) and differ-
ential nonlinearity (DNL) of ±1/4LSB. The ability to
interface directly with baseband I and Q signals makes
the MAX1002 ideal for use in direct-broadcast satellite,
VSAT, and QAM16 demodulation applications.
The MAX1002 input amplifiers feature true differential
inputs, a 55MHz -0.5dB analog bandwidth, and user-
programmable input full-scale ranges of 125mVp-p,
250mVp-p, or 500mVp-p. With an AC-coupled input
signal, matching performance between input channels
is typically 0.1dB gain, 1/4LSB offset, and 0.5° phase.
Dynamic performance is 5.85 effective number of bits
(ENOB) with a 20MHz analog input signal, or 5.78
ENOB with a 50MHz input signal.
The MAX1002 operates with a single +5V power supply
and provides TTL-compatible digital outputs. The device
is available in the commercial temperature range (0°C to
+70°C) and comes in a 36-pin SSOP package.
________________________Applications
____________________________Features
o ±1/4LSB INL and DNL, Typical
o 1/4LSB (typ) Channel-to-Channel Offset Matching
o 0.1dB Gain and 0.5° Phase Matching, Typical
o Internal Bandgap Voltage Reference
o Two Matched 6-Bit, 60Msps ADCs
o Excellent Dynamic Performance:
5.85 ENOB with 20MHz Analog Input
5.7 ENOB with 50MHz Analog Input
o Internal Oscillator with Overdrive Capability
o 55MHz (-0.5dB) Bandwidth Input Amplifiers
with True Differential Inputs
o User-Selectable Input Full-Scale Range
(125mVp-p, 250mVp-p, or 500mVp-p)
o Single-Ended or Differential Input Drive
o +5V Single Supply
o TTL Outputs
o 90Msps Upgrade with +3.3V CMOS-Compatible
Output Available (MAX1003)
______________Ordering Information
Direct Broadcast Satellite (DBS) Receivers
VSAT Receivers
Wide Local Area Networks (WLAN)
Cable Television Set-Top Boxes
PART
MAX1002CAX
TEMP. RANGE
0°C to +70°C
PIN-PACKAGE
36 SSOP
Pin Configuration appears at end of data sheet.
_________________________________________________________Functional Diagram
IOCC+
IOCC-
IIN+
INPUT
AMP
IIN- I
OFFSET
CORREC-
TION I
ADC
I
VREF
6
DATA
BUFFER
I
6
CLOCK
OUT
D0I–D5I
DCLK
GAIN
QIN+
QIN-
INPUT
AMP
Q
OFFSET
CORREC-
TION Q
BANDGAP
REFERENCE
VREF
ADC
Q
CLOCK
DRIVER
MAX1002
6
DATA
6
BUFFER
Q
TNK+
TNK-
DQ0–DQ5
QOCC+
QOCC-
________________________________________________________________ Maxim Integrated Products 1
For free samples & the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800
For small orders, phone 408-737-7600 ext. 3468.



Maxim Integrated Semiconductor Electronic Components Datasheet

MAX1002 Datasheet

Low-Power / 60Msps / Dual / 6-Bit ADC

No Preview Available !

MAX1002 pdf
Low-Power, 60Msps, Dual, 6-Bit ADC
ABSOLUTE MAXIMUM RATINGS
VCC to GND .........................................................-0.3V to +6.5V
VCCO to OGND.........................................................-0.3V, +6.5V
GND to OGND .........................................................-0.3V, +0.3V
Digital and Clock Output Pins to OGND ........-0.3V, VCCO (<10sec)
All Other Pins to GND..................................................-0.3V, VCC
Continuous Power Dissipation (TA = +70°C)
SSOP (derate 45mW/°C above +70°C) ......................941mW
Operating Temperature Range...............................0°C to +70°C
Storage Temperature Range .............................-65°C to +150°C
Lead Temperature (soldering, <10sec)...........................+300°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
(VCC, VCCO = +5V ±5%; TA = TMIN to TMAX; unless otherwise noted.)
PARAMETER
SYMBOL
CONDITIONS
DC ACCURACY (Note 1)
Resolution
RES
Integral Nonlinearity
INL
Differential Nonlinearity
DNL No missing codes over temperature
VFSH GAIN = VCC (high gain)
Full-Scale Input Range
VFSM GAIN = open (mid gain)
VFSL GAIN = GND (low gain)
INVERTING AND NONINVERTING ANALOG INPUTS
Input Open-Circuit Voltage
Input Resistance
Input Capacitance
VAOC
RIN
CIN
Guaranteed by design
Common-Mode Voltage Range
VCM
Other analog input driven with external source
(Note 2)
OSCILLATOR INPUTS
Oscillator Input Resistance
ROSC Other oscillator input tied to VCC + 0.3V
DIGITAL OUTPUTS (DI0–DI5, DQ0–DQ5)
Digital Outputs Logic-High
Voltage
VOH
ISOURCE = 50µA
MIN
6
-0.5
-0.5
118.75
237.5
475
2.25
13
1.75
4.8
2.4
Digital Outputs Logic-Low
Voltage
POWER SUPPLY
Supply Current
Power-Supply Rejection Ratio
Digital Outputs Supply Current
Power Dissipation
VOL ISINK = 400µA
ICC
PSRR
ICCO
PD
VCC = 4.75V to 5.25V (Note 3)
20MHz, FS I & Q analog inputs,
CLOAD = 15pF (Note 4)
TYP
±0.25
±0.25
125
250
500
2.35
20
3
8
63
-75
380
MAX UNITS
0.5
0.5
131.25
262.5
525
Bits
LSB
LSB
mVp-p
2.45 V
29 k
5 pF
2.75 V
12.1 k
V
0.5 V
104 mA
-40 dB
24 mA
mW
2 _______________________________________________________________________________________



Maxim Integrated Semiconductor Electronic Components Datasheet

MAX1002 Datasheet

Low-Power / 60Msps / Dual / 6-Bit ADC

No Preview Available !

MAX1002 pdf
Low-Power, 60Msps, Dual, 6-Bit ADC
AC ELECTRICAL CHARACTERISTICS
(VCC, VCCO = +5V ±5%; TA = +25°C; unless otherwise noted.)
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX UNITS
DYNAMIC PERFORMANCE (GAIN = open; external 60MHz clock (Figure 7); VINI, VINIQ = 20MHz sine; amplitude -1dB below FS;
unless otherwise noted.)
Maximum Sample Rate
Analog Input -0.5dB Bandwidth
Effective Number of Bits
Signal-to-Noise and Distortion
Ratio
fMAX
BW
ENOBM
ENOBH
ENOBL
SINAD
Gain = GND, open, VCC
GAIN = open (mid gain)
GAIN = open (mid gain),
VIN = 50MHz, -1dB below FS
Gain = VCC (high gain)
Gain = VCC (low gain)
Gain = open (mid gain)
60
55
5.6 5.85
5.7
5.8
5.85
35.4 37
Msps
MHz
Bits
dB
Input Offset (Note 5)
OFF
Crosstalk Between ADCs
XTLK
Offset Mismatch Between ADCs OMM2
I channel
Q channel
(Note 5)
-0.5
-0.5
-55
-0.5 ±0.25
0.5
0.5
0.5
LSB
dB
LSB
Amplitude Match Between
ADCs
AM
-0.2 ±0.1 0.2
dB
Phase Match Between ADCs
PM
TIMING CHARACTERISTICS (data outputs: RL = 1M, CL = 15pF, Figure 8)
DCLK to Data-Propagation
Delay
tPD (Note 6)
-2 ±0.5
2 degrees
7.1 ns
Data Valid Skew
Input to DCLK Delay
Aperture Delay
Pipeline Delay
tSKEW
tDCLK
tAP
PD
(Note 6)
TNK+ to DCLK (Note 6)
3.6 ns
5.3 ns
5.5 ns
1
clock
cycle
Note 1: Best straight-line linearity method.
Note 2: A typical application will AC couple the analog input to the DC bias level present at the analog inputs (typically 2.35V).
However, it is also possible to DC couple the analog input (using differential or single-ended drive) within this common-
mode input range (Figures 4, 5).
Note 3: PSSR is defined as the change in the mid-gain, full-scale range as a function of the variation in VCC supply voltage
(expressed in decibels).
Note 4: The current in the VCCO supply is a strong function of the capacitive loading on the digital outputs. To minimize supply
transients and achieve the best dynamic performance, reduce the capacitive loading effects by keeping line lengths on the
digital outputs to a minimum.
Note 5: Offset-correction compensation enabled, 0.22µF at Q and I compensation inputs (Figures 2, 3).
Note 6: tPD and tSKEW are measured from the 1.4V level of the output clock, to the 1.4V level of either the rising or falling edge of a
data bit. tDCLK is measured from the 50% level of the clock overdrive signal on TNK+ to the 1.4V level of DCLK. The capac-
itive load on the outputs is 15pF.
_______________________________________________________________________________________ 3




Part Number MAX1002
Description Low-Power / 60Msps / Dual / 6-Bit ADC
Maker Maxim
Total Page 12 Pages
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