http://www.www.datasheet4u.com

900,000+ Datasheet PDF Search and Download

Datasheet4U offers most rated semiconductors datasheets pdf



Intersil Electronic Components Datasheet

ID82C284 Datasheet

Clock Generator and Ready Interface for 80C286 Processors

No Preview Available !

ID82C284 pdf
82C284
March 1997
Clock Generator and Ready Interface
for 80C286 Processors
Features
• Generates System Clock for 80C286 Processors
• Generates System Reset Output from Schmitt
Trigger Input
- Improved Hysteresis
• Uses Crystal or External Signal for Frequency Source
• Dynamically Switchable between Two Input
Frequencies
• Provides Local READY and MULTIBUS® READY
Synchronization
• Static CMOS Technology
• Single +5V Power Supply
• Available in 18 Lead CerDIP Package
Description
The Intersil 82C284 is a clock generator/driver which
provides clock signals for 80C286 processors and support
components. It also contains logic to supply READY to the
CPU from either asynchronous or synchronous sources and
synchronous RESET from an asynchronous input with
hysteresis.
Ordering Information
PART NUMBER
CD82C284-12
ID82C284-10
ID82C284-12
TEMP. RANGE
0oC to +70oC
-40oC to +85oC
-40oC to +85oC
PACKAGE
PKG.
NO.
18 Ld CERDIP F18.3
18 Ld CERDIP F18.3
18 Ld CERDIP F18.3
Pinout
82C284 (CERDIP)
TOP VIEW
ARDY 1
SRDY 2
SRDYEN 3
READY 4
EFI 5
F/C 6
X1 7
X2 8
GND 9
18 VCC
17 ARDYEN
16 S1
15 S0
14 NC
13 PCLK
12 RESET
11 RES
10 CLK
Functional Diagram
RES
X1
X2
EFI
F/C
ARDYEN
ARDY
SRDYEN
SRDY
S1
S0
RESET
SYNCHRONIZER
XTAL
OSC
MUX
SYNCHRONIZER
READY LOGIC
PCLK GENERATOR
RESET
CLK
READY
PCLK
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
MULTIBUS® is a patented Intel bus.
1
File Number 2966.1



Intersil Electronic Components Datasheet

ID82C284 Datasheet

Clock Generator and Ready Interface for 80C286 Processors

No Preview Available !

ID82C284 pdf
82C284
Pin Description The following pin function descriptions are for the 82C284 clock generator.
PIN
SYMBOL NUMBER TYPE
DESCRIPTION
CLK 10
O SYSTEM CLOCK: the signal used by the processor and support devices which must be synchro-
nous with the processor. The frequency of the CLK output has twice the desired internal processor
clock frequency. CLK can drive both TTL and CMOS level inputs.
F/C 6
I FREQUENCY/CRYSTAL SELECT: this pin selects the source for the CLK output. When there is a
LOW level on this input, the internal crystal oscillator drives CLK. When there is a HIGH level on F/C,
the EFI input drives the CLK input. This pin can be dynamically switched, which allows changing the
processor CLK frequency while running for low-power operation, etc.
X1, X2
7, 8
I CRYSTAL IN: the pin stop which parallel resonant, fundamental mode crystal is attached for the in-
ternal oscillator. When F/C is LOW, the internal oscillator will drive the CLK output at the crystal fre-
quency. The crystal frequency must be twice the desired internal processor clock frequency.
EFI 5
I EXTERNAL FREQUENCY IN: drives CLK when the F/C input is HIGH. The EFI input frequency
must be twice the desired internal processor clock frequency.
PCLK
13
O PERIPHERAL CLOCK: the output which provides a 50% duty cycle clock with one-half the frequen-
cy of CLK. PCLK will be in phase with the internal processor clock following the first bus cycle after
the processor has been reset.
ARDYEN
17
I ASYNCHRONOUS READY ENABLE: an active LOW input which qualifies the ARDY input.
ARDYEN selects ARDY as the source of READY for the current bus cycle. Inputs to ARDYEN may
be applied asynchronously to CLK. Setup and hold times are given to assure a guaranteed response
to synchronous outputs.
ARDY
1
I ASYNCHRONOUS READY: an active LOW input used to terminate the current bus cycle. The ARDY
input is qualified by ARDYEN. Inputs to ARDY may be applied asynchronously to CLK. Setup and
hold times are given to assure a guaranteed response to synchronous outputs.
SRDYEN
3
I SYNCHRONOUS READY ENABLE: an active LOW input which qualifies SRDY. SRDYEN selects
SRDY as the source for READY to the CPU for the current bus cycle. Setup and hold time must be
satisfied for proper operation.
SRDY
2
I SYNCHRONOUS READY: an active LOW input used to terminate the current bus cycle. The SRDY
input is qualified by the SRDYEN input. Setup and hold time must be satisfied for proper operation.
READY
4
O READY: an active LOW output which signals to the processor that the current bus cycle is to be com-
pleted. The SRDY SRDYEN, ARDY, ARDYEN, S1, S0, and RES inputs control READY as explained
later in the READY generator section. READY is an open drain output requiring an external pull-up
resistor.
S0, S1
15,16
I STATUS: these inputs prepare the 82C284 for a subsequent bus cycle. S0 and S1 synchronize
PCLK to the internal processor clock and control READY. Setup and hold times must be satisfied for
proper operation
RESET
12
O RESET: an active HIGH output which is derived from the RES input RESET is used to force the sys-
tem into an initial state. When RESET is active, READY will be active (LOW).
RES
11
I RESET IN: an active LOW input which generates the system reset signal (RESET). Signals to RES
may be applied asynchronously to CLK. A Schmitt trigger input is provided on RES, so that an RC
circuit can be used to provide a time delay. Setup and hold times are given to assure a guaranteed
response to synchronous inputs.
VCC
18
SYSTEM POWER: The +5V Power Supply Pin. A 0.1µF capacitor between VCC and GND is recom-
mended for decoupling.
GND
9
SYSTEM GROUND: 0V
2



Intersil Electronic Components Datasheet

ID82C284 Datasheet

Clock Generator and Ready Interface for 80C286 Processors

No Preview Available !

ID82C284 pdf
82C284
Functional Description
Introduction
The 82C284 generates the clock, ready, and reset signals
required for 80C286 processors and support components.
The 82C284 is packaged in an 18-pin DIP and contains a
crystal controlled oscillator, clock generator, peripheral clock
generator, MULTIBUS® ready synchronization logic, and
system reset generation logic.
Clock Generator
The CLK output provides the basic timing control for an
80C286 system. CLK has output characteristics sufficient to
drive CMOS devices. CLK is generated by either an internal
crystal oscillator, or an external source as selected by the
F/C input pin. When F/C is LOW, the crystal oscillator drives
the CLK output. When F/C is HIGH, the EFI input drives the
CLK output.
The F/C pin on the Intersil 82C284 is dynamically switch-
able. This allows the CLK frequency to the processor to be
changed from one frequency to another in a running system.
With this feature, a system can be designed which operates
at maximum speed when needed, and then dynamically
switched to a lower frequency to implement a low-power
mode. The lower frequency can be anything down to, but
excluding, DC. The following 3 conditions apply when
dynamically switching the F/C pin (see Figure 1):
1) The CLK is stretched in the low portion of the φ2 phase
of its cycle during transition from one CLK frequency to
the other (see Waveforms).
2) When switching CLK frequency sources, there is a max-
imum transition latency of 2.5 clock cycles of the fre-
quency being switched to, from the time CLK freezes
low, until CLK restarts at the new frequency (see Wave-
forms).
3) The maximum latency from the time F/C is dynamically
switched, to the time CLK freezes low, is 4 CLK cycles
(see Waveforms).
The following steps describe the sequence of events that
transpire when F/C is dynamically switched:
A) F/C switched from high (using EFI input) to low (using
the crystal input X1 - see Figure 1A).
1) The state of F/C is sampled when both CLK and
PCLK are high until a change is detected.
2) On the second following falling edge of PCLK, CLK is
frozen low.
3) CLK restarts at the crystal frequency on the rising
edge of Xl, after the second falling edge of X1.
B) F/C switched from low (using the crystal input Xl) to high
(using the EFI input - see Figure 1B).
1) The state of F/C is sampled when both CLK and
PCLK are high until a change is detected.
2) On the second following falling edge of PCLK, CLK is
frozen low.
3) CLK restarts at the EFI input frequency on the falling
edge of EFl after the second rising edge of EFI.
CLK
φ1
1
φ2
φ1
φ2 φ1 φ2
PCLK
2
F/C
X1
3
FIGURE 1A. F/C SWITCHED FROM HIGH (USING EFI INPUT) TO LOW (USING THE CRYSTAL INPUT X1)
3




Part Number ID82C284
Description Clock Generator and Ready Interface for 80C286 Processors
Maker Intersil Corporation
Total Page 11 Pages
PDF Download
ID82C284 pdf
Download PDF File
ID82C284 pdf
View for Mobile






Related Datasheet

1 ID82C284 Clock Generator and Ready Interface for 80C286 Processors Intersil Corporation
Intersil Corporation
ID82C284 pdf




Part Number Start With

0    1    2    3    4    5    6    7    8    9    A    B    C    D    E    F    G    H    I    J    K    L    M    N    O    P    Q    R    S    T    U    V    W    X    Y    Z

site map

webmaste! click here

contact us

Buy Components