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Intersil Electronic Components Datasheet

ICL8049 Datasheet

Antilog Amplifier

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ICL8049 pdf
July 1999
Features
®
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ICL8049
Antilog Amplifier
• Full Scale Accuracy . . . . . . . . . . . . . . . . . . . . . . . . . 0.5%
• Temperature Compensated Operation . . . . 0oC to 70oC
• Scale Factor, Adjustable . . . . . . . . . . . . . . . . 1V/Decade
• Dynamic Voltage Range . . . . . . . . . . . . . . . . . . . . .60dB
The ICL8049 is a monolithic antilogarithmic amplifier that is
fully temperature compensated and is nominally designed to
provide 1 decade of output voltage for each 1V change of
input voltage. For increased flexibility, the scale factor, refer-
ence current and offset voltage are externally adjustable.
• Dual JFET Input Op Amps
Part Number Information
PART NUMBER
ICL8049BCJE
ICL8049CCJE
ERROR (25oC)
10mV
25mV
TEMPERATURE RANGE (oC)
0 to 70
0 to 70
PACKAGE
16 Ld CERDIP
16 Ld CERDIP
Pinout
ICL8049 (CERDIP)
TOP VIEW
A1 INPUT 1
GAIN 2
IREF
A1 OFFSET
NULL
A1 OFFSET
NULL
V-
3
4
5
6
A1 OUTPUT 7
NC 8
16 VIN
15 GND
14 A2 INPUT
13
A2 OFFSET
NULL
12 A2 OFFSET
NULL
11 V+
10 VOUT
9 NC
Functional Diagram
VREF
ICL8049
3 IREF
VIN
16
GAIN
2
Q1 Q2
--
A1 A2
++
1
A1 INPUT
7
A1 OUTPUT
15
GND
A2 INPUT
14 fOUT
10
VOUT
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CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2002. All Rights Reserved
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File Number 4768



Intersil Electronic Components Datasheet

ICL8049 Datasheet

Antilog Amplifier

No Preview Available !

ICL8049 pdf
ICL8049
Absolute Maximum Ratings
Operating Conditions
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±18V
VIN (Input Current) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±15V
IREF (Reference Current) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2mA
Voltage Between Offset Null and V+ . . . . . . . . . . . . . . . . . . . ±0.5V
Output Short Circuit Duration . . . . . . . . . . . . . . . . . . . . . . . Indefinite
Power Dissipation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 750mW
Lead Temperature (Soldering 10 Sec.) . . . . . . . . . . . . . . . . . 300oC
Operating Temperature Range . . . . . . . . . . . . . . . . . . . 0oC to 70oC
Storage Temperature Range . . . . . . . . . . . . . . . . . . -65oC to 150oC
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Electrical Specifications VS = ±15V, TA = 25oC, IREF = 1mA, Scale Factor Adjusted for 1 Decade (Out) per Volt (In), Unless Oth-
erwise Specified
PARAMETERS
TEST CONDITIONS
Dynamic Range (VOUT)
Error, Absolute Value
Temperature Coefficient, Referred
to VIN
Power Supply Rejection Ratio
Offset Voltage (A1 and A2)
Wideband Noise
Output Voltage Swing
Power Consumption
VOUT = 10mV to 10V
0V VIN 2V
TA = 0oC to 70oC,
0V VIN 3V
VIN = 3V
Referred to Input,
for VIN = 0V
Before Nulling
Referred to Input,
for VIN = 0V
RL = 10k
RL = 2k
Supply Current
ICL4049BC
MIN TYP MAX
60 -
-
- 3 15
- 20 75
ICL8049CC
MIN TYP MAX
60 -
-
- 5 25
- 30 150
UNITS
dB
mV
mV
- 0.38 -
- 0.55 -
mV/oC
- 2.0 -
- 2.0 -
µV/V
- 15 25
- 26 -
±12 ±14
-
±10 ±13
-
- 150 200
- 5 6.7
- 15 50
- 26 -
±12 ±14
-
±10 ±13
-
- 150 200
- 5 6.7
mV
µVRMS
V
V
mW
mA
2



Intersil Electronic Components Datasheet

ICL8049 Datasheet

Antilog Amplifier

No Preview Available !

ICL8049 pdf
ICL8049
V+
R4
2k
R3
15k
VIN
R6
100k
R5
15k
680
(LOW
T.C.)
1k
R2
R1
15.9k
2
16
V- 1
-
A1
+
VREF
(+15V)
RREF
C1 15k
7 200pF 3
IREF
Q1 Q2
+
A2
-
14
IOUT
ROUT
10k
10
VOUT
15 12 R7 13
2k
V+
FIGURE 1. ICL8049 OFFSET AND SCALE FACTOR ADJUSTMENT
ICL8049 Detailed Description
The ICL8049 relies on the same logarithmic properties of
the transistor as the ICL8048. The input voltage forces a
specific VBE between Q1 and Q2 (Figure 1). This VBE
difference is converted into a difference of collector currents
by the transistor pair. The equation governing the behavior
of the transistor pair is derived from (2) on the previous page
and is as follows:
II--CC----12-- = exp q------k--V-T--B----E--
(1)
When numerical values for q/kT are put into this equation, it
is found that a VBE of 59mV (at +25oC) is required to
change the collector current ratio by a factor of ten. But for
ease of application, it is desirable that a 1V change at the
input generate a tenfold change at the output. The required
input attenuation is achieved by the network comprising R1
and R2. In order that scale factors other than one decade
per volt may be selected, R2 is external to the chip. It should
have a value of 1k, adjustable ±20%, for one decade per
volt. R1 is a thin film resistor deposited on the monolithic
chip; its temperature characteristics are chosen to
compensate the temperature dependence of Equation 1, as
explained on the previous page.
The overall transfer function is as follows:
I-I-OR---UE---FT-
=
exp
(---R---1-----R+---2--R---2---)
×
q---V---I--N-
kT
Substituting VOUT = IOUT x ROUT gives:
VOUT = ROUT IREF exp (---R----1-–---R+----2-R----2----) × q----kV--T-I--N---
(2)
(3)
For voltage references Equation 3 becomes
VOUT
=
VREF × -RR---OR---UE---FT- exp
(---R---1-–---+R---2-R----2--)-
×
q---V---I-N--
kT
(4)
ICL8049 Offset and Scale Factor
Adjustment
As with the log amplifier, the antilog amplifier requires three
adjustments. The first step is to null out the offset voltage of
A2. This is accomplished by reverse biasing the base-emitter
of Q2. A2 then operates as a unity gain buffer with a
grounded input. The second step forces VIN = 0; the output is
adjusted for VOUT = 10V. This step essentially “anchors” one
point on the transfer function. The third step applies a
specific input and adjusts the output to the correct voltage.
This sets the scale factor. Referring to Figure 1 the exact
procedure for 1 decade/volt is as follows:
1. Connect the input (pin #16) to +15V. This reverse biases
the base-emitter of Q2. Adjust R7 for VOUT = 0V. Discon-
nect the input from +15V.
2. Connect the input to Ground. Adjust R4 for VOUT = 10V.
Disconnect the input from Ground.
3. Connect the input to a precise 2V supply and adjust R2 for
VOUT = 100mV.
The procedure outlined above optimizes the performance
over a 3 decade range at the output (i.e., VOUT from 10mV)
to 10V). For a more limited range of output voltages, for
example 1V to 10V, it would be better to use a precise 1V
supply and adjust for VOUT = 1V. For other scale factors and/
or starting points, different values for R2 and RREF will be
needed, but the same basic procedure applies.
3




Part Number ICL8049
Description Antilog Amplifier
Maker Intersil Corporation
Total Page 3 Pages
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