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Intersil Electronic Components Datasheet

4015B Datasheet

CMOS Dual 4-Stage Static Shift Register With Serial Input/Parallel Output

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4015B pdf
CD4015BMS
December 1992
CMOS Dual 4-Stage Static Shift Register
With Serial Input/Parallel Output
Features
Pinout
• High-Voltage Type (20V Rating)
• Medium Speed Operation 12MHz (typ.) Clock Rate at
VDD - VSS = 10V
• Fully Static Operation
• 8 Master-Slave Flip-Flops Plus Input and Output Buffering
• 100% Tested For Quiescent Current at 20V
• 5V, 10V and 15V Parametric Ratings
• Standardized Symmetrical Output Characteristics
• Maximum Input Current of 1µA at 18V Over Full Pack-
age-Temperature Range; 100nA at 18V and 25oC
• Noise Margin (Full Package-Temperature Range) =
- 1V at VDD = 5V
- 2V at VDD = 10V
- 2.5V at VDD = 15V
• Meets All Requirements of JEDEC Tentative Standard
No. 13B, “Standard Specifications for Description of
‘B’ Series CMOS Devices”
Applications
• Serial-Input/Parallel-Output Data Queueing
• Serial to Parallel Data Conversion
• General-Purpose Register
Description
CD4015BMS consists of two identical, independent, 4-stage
serial-input/parallel output registers. Each register has inde-
pendent CLOCK and RESET inputs as well as a single serial
DATA input. “Q” outputs are available from each of the four
stages on both registers. All register stages are D type, mas-
ter-slave flip-flops. The logic level present at the DATA input
is transferred into the first register stage and shifted over one
stage at each positive-going clock transition. Resetting of all
stages is accomplished by a high level on the reset line.
Register expansion to 8 stages using one CD4015BMS
package, or to more than 8 stages using additional
CD4015BMS’s is possible.
The CD4015BMS is supplied in these 16 lead outline pack-
ages:
CD4015BMS
TOP VIEW
CLOCK B 1
Q4B 2
Q3A 3
Q2A 4
Q1A 5
RESET A 6
DATA A 7
VSS 8
16 VDD
15 DATA B
14 RESET B
13 Q1B
12 Q2B
11 Q3B
10 Q4A
9 CLOCK A
Functional Diagram
DATA A
CLOCK A
RESET A
7
9
6
DATA B
CLOCK B
RESET B
15
1
14
VDD
16
4
STAGE
4
STAGE
5
Q1A
4
Q2A
3 Q3A
10 Q4A
13
Q1B
12
Q2B
11
Q3B
2
Q4B
8
VSS
Braze Seal DIP H4X
Frit Seal DIP
H1F
Ceramic Flatpack H6W
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
7-89
File Number 3295



Intersil Electronic Components Datasheet

4015B Datasheet

CMOS Dual 4-Stage Static Shift Register With Serial Input/Parallel Output

No Preview Available !

4015B pdf
Specifications CD4015BMS
Absolute Maximum Ratings
DC Supply Voltage Range, (VDD) . . . . . . . . . . . . . . . -0.5V to +20V
(Voltage Referenced to VSS Terminals)
Input Voltage Range, All Inputs . . . . . . . . . . . . .-0.5V to VDD +0.5V
DC Input Current, Any One Input . . . . . . . . . . . . . . . . . . . . . . . .±10mA
Operating Temperature Range . . . . . . . . . . . . . . . . -55oC to +125oC
Package Types D, F, K, H
Storage Temperature Range (TSTG) . . . . . . . . . . . -65oC to +150oC
Lead Temperature (During Soldering) . . . . . . . . . . . . . . . . . +265oC
At Distance 1/16 ± 1/32 Inch (1.59mm ± 0.79mm) from case for
10s Maximum
Reliability Information
Thermal Resistance . . . . . . . . . . . . . . . .
θja
Ceramic DIP and FRIT Package . . . . . 80oC/W
θjc
20oC/W
Flatpack Package . . . . . . . . . . . . . . . . 70oC/W
20oC/W
Maximum Package Power Dissipation (PD) at +125oC
For TA = -55oC to +100oC (Package Type D, F, K) . . . . . . 500mW
For TA = +100oC to +125oC (Package Type D, F, K) . . . . . Derate
Linearity at 12mW/oC to 200mW
Device Dissipation per Output Transistor . . . . . . . . . . . . . . . 100mW
For TA = Full Package Temperature Range (All Package Types)
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175oC
TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS
PARAMETER
SYMBOL
CONDITIONS (NOTE 1)
GROUP A
SUBGROUPS TEMPERATURE
LIMITS
MIN MAX UNITS
Supply Current
IDD VDD = 20V, VIN = VDD or GND
1
+25oC
- 10 µA
2
+125oC
- 1000 µA
VDD = 18V, VIN = VDD or GND
3
-55oC
- 10 µA
Input Leakage Current
IIL VIN = VDD or GND VDD = 20
1
+25oC
-100
-
nA
2
+125oC
-1000 -
nA
VDD = 18V
3
-55oC
-100
-
nA
Input Leakage Current
IIH VIN = VDD or GND VDD = 20
1
+25oC
- 100 nA
2
+125oC
- 1000 nA
VDD = 18V
3
-55oC
- 100 nA
Output Voltage
VOL15 VDD = 15V, No Load
1, 2, 3
+25oC, +125oC, -55oC -
50 mV
Output Voltage
VOH15 VDD = 15V, No Load (Note 3)
1, 2, 3
+25oC, +125oC, -55oC 14.95
-
V
Output Current (Sink)
IOL5 VDD = 5V, VOUT = 0.4V
1
+25oC
0.53 - mA
Output Current (Sink)
IOL10 VDD = 10V, VOUT = 0.5V
1
+25oC
1.4 - mA
Output Current (Sink)
IOL15 VDD = 15V, VOUT = 1.5V
1
+25oC
3.5 - mA
Output Current (Source) IOH5A VDD = 5V, VOUT = 4.6V
1
+25oC
- -0.53 mA
Output Current (Source) IOH5B VDD = 5V, VOUT = 2.5V
1
+25oC
- -1.8 mA
Output Current (Source) IOH10 VDD = 10V, VOUT = 9.5V
1
+25oC
- -1.4 mA
Output Current (Source) IOH15 VDD = 15V, VOUT = 13.5V
1
+25oC
- -3.5 mA
N Threshold Voltage
VNTH VDD = 10V, ISS = -10µA
1
+25oC
-2.8 -0.7 V
P Threshold Voltage
VPTH VSS = 0V, IDD = 10µA
1
+25oC
0.7 2.8
V
Functional
F VDD = 2.8V, VIN = VDD or GND
VDD = 20V, VIN = VDD or GND
7
7
+25oC
+25oC
VOH > VOL < V
VDD/2 VDD/2
VDD = 18V, VIN = VDD or GND
8A
+125oC
VDD = 3V, VIN = VDD or GND
8B
-55oC
Input Voltage Low
(Note 2)
VIL VDD = 5V, VOH > 4.5V, VOL < 0.5V 1, 2, 3 +25oC, +125oC, -55oC -
1.5 V
Input Voltage High
(Note 2)
VIH VDD = 5V, VOH > 4.5V, VOL < 0.5V 1, 2, 3 +25oC, +125oC, -55oC 3.5
-
V
Input Voltage Low
(Note 2)
VIL VDD = 15V, VOH > 13.5V,
VOL < 1.5V
1, 2, 3
+25oC, +125oC, -55oC -
4V
Input Voltage High
(Note 2)
VIH VDD = 15V, VOH > 13.5V,
VOL < 1.5V
1, 2, 3
+25oC, +125oC, -55oC 11
-
V
NOTES: 1. All voltages referenced to device GND, 100% testing being 3. For accuracy, voltage is measured differentially to VDD. Limit
implemented.
is 0.050V max.
2. Go/No Go test with limits applied to inputs
7-90



Intersil Electronic Components Datasheet

4015B Datasheet

CMOS Dual 4-Stage Static Shift Register With Serial Input/Parallel Output

No Preview Available !

4015B pdf
Specifications CD4015BMS
TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS
PARAMETER
Propagation Delay
Clock To Q
Propagation Delay
Reset To Q
Transition Time
Maximum Clock Input
Frequency
SYMBOL CONDITIONS (NOTE 1, 2)
TPHL1 VDD = 5V, VIN = VDD or GND
TPLH1
TPHL2 VDD = 5V, VIN = VDD or GND
TTHL VDD = 5V, VIN = VDD or GND
TTLH
FCL VDD = 5V, VIN = VDD or GND
GROUP A
SUBGROUPS TEMPERATURE
9 +25oC
10, 11
+125oC, -55oC
9 +25oC
10, 11
+125oC, -55oC
9 +25oC
10, 11
+125oC, -55oC
9 +25oC
10, 11
+125oC, -55oC
LIMITS
MIN MAX
- 320
- 432
- 400
- 540
- 200
- 270
3-
3/1.35
-
NOTES:
1. CL = 50pF, RL = 200K, Input TR, TF < 20ns.
2. -55oC and +125oC limits guaranteed, 100% testing being implemented.
UNITS
ns
ns
ns
ns
ns
ns
MHz
MHz
TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS
PARAMETER
Supply Current
SYMBOL
CONDITIONS
IDD VDD = 5V, VIN = VDD or GND
VDD = 10V, VIN = VDD or GND
VDD = 15V, VIN = VDD or GND
Output Voltage
Output Voltage
Output Voltage
Output Voltage
Output Current (Sink)
VOL VDD = 5V, No Load
VOL VDD = 10V, No Load
VOH VDD = 5V, No Load
VOH VDD = 10V, No Load
IOL5 VDD = 5V, VOUT = 0.4V
Output Current (Sink)
IOL10 VDD = 10V, VOUT = 0.5V
Output Current (Sink)
IOL15 VDD = 15V, VOUT = 1.5V
Output Current (Source) IOH5A VDD = 5V, VOUT = 4.6V
Output Current (Source) IOH5B VDD = 5V, VOUT = 2.5V
Output Current (Source) IOH10 VDD = 10V, VOUT = 9.5V
Output Current (Source) IOH15 VDD =15V, VOUT = 13.5V
Input Voltage Low
VIL VDD = 10V, VOH > 9V, VOL < 1V
NOTES
1, 2
1, 2
1, 2
1, 2
1, 2
1, 2
1, 2
1, 2
1, 2
1, 2
1, 2
1, 2
1, 2
1, 2
1, 2
TEMPERATURE
-55oC, +25oC
+125oC
-55oC, +25oC
+125oC
-55oC, +25oC
+125oC
+25oC, +125oC,
-55oC
+25oC, +125oC,
-55oC
+25oC, +125oC,
-55oC
+25oC, +125oC,
-55oC
+125oC
-55oC
+125oC
-55oC
+125oC
-55oC
+125oC
-55oC
+125oC
-55oC
+125oC
-55oC
+125oC
-55oC
+25oC, +125oC,
-55oC
LIMITS
MIN MAX
-5
- 150
- 10
- 300
- 10
- 600
- 50
- 50
4.95 -
9.95 -
0.36 -
0.64 -
0.9 -
1.6 -
2.4 -
4.2 -
- -0.36
- -0.64
- -1.15
- -2.0
- -0.9
- -1.6
- -2.4
- -4.2
-3
UNITS
µA
µA
µA
µA
µA
µA
mV
mV
V
V
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
V
7-91




Part Number 4015B
Description CMOS Dual 4-Stage Static Shift Register With Serial Input/Parallel Output
Maker Intersil Corporation
Total Page 8 Pages
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