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Intel Corporation
Intel Corporation

E28F010-65 Datasheet Preview

E28F010-65 Datasheet

1024K (128K x 8) CMOS FLASH MEMORY

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E28F010-65 pdf
28F010
1024K (128K x 8) CMOS FLASH MEMORY
Y Flash Electrical Chip-Erase
1 Second Typical Chip-Erase
Y Quick Pulse Programming Algorithm
10 ms Typical Byte-Program
2 Second Chip-Program
Y 100 000 Erase Program Cycles
Y 12 0V g5% VPP
Y High-Performance Read
65 ns Maximum Access Time
Y CMOS Low Power Consumption
10 mA Typical Active Current
50 mA Typical Standby Current
0 Watts Data Retention Power
Y Integrated Program Erase Stop Timer
Y Command Register Architecture for
Microprocessor Microcontroller
Compatible Write Interface
Y Noise Immunity Features
g10% VCC Tolerance
Maximum Latch-Up Immunity
through EPI Processing
Y ETOXTM Nonvolatile Flash Technology
EPROM-Compatible Process Base
High-Volume Manufacturing
Experience
Y JEDEC-Standard Pinouts
32-Pin Plastic Dip
32-Lead PLCC
32-Lead TSOP
(See Packaging Spec Order 231369)
Y Extended Temperature Options
Intel’s 28F010 CMOS flash memory offers the most cost-effective and reliable alternative for read write
random access nonvolatile memory The 28F010 adds electrical chip-erasure and reprogramming to familiar
EPROM technology Memory contents can be rewritten in a test socket in a PROM-programmer socket on-
board during subassembly test in-system during final test and in-system after-sale The 28F010 increases
memory flexibility while contributing to time and cost savings
The 28F010 is a 1024 kilobit nonvolatile memory organized as 131 072 bytes of 8 bits Intel’s 28F010 is
offered in 32-pin plastic dip or 32-lead PLCC and TSOP packages Pin assignments conform to JEDEC
standards for byte-wide EPROMs
Extended erase and program cycling capability is designed into Intel’s ETOX (EPROM Tunnel Oxide) process
technology Advanced oxide processing an optimized tunneling structure and lower electric field combine to
extend reliable cycling beyond that of traditional EEPROMs With the 12 0V VPP supply the 28F010 performs
100 000 erase and program cycles well within the time limits of the Quick Pulse Programming and Quick Erase
algorithms
Intel’s 28F010 employs advanced CMOS circuitry for systems requiring high-performance access speeds low
power consumption and immunity to noise Its 65 nanosecond access time provides no-WAIT-state perform-
ance for a wide range of microprocessors and microcontrollers Maximum standby current of 100 mA trans-
lates into power savings when the device is deselected Finally the highest degree of latch-up protection is
achieved through Intel’s unique EPI processing Prevention of latch-up is provided for stresses up to 100 mA
on address and data pins from b1V to VCC a 1V
With Intel’s ETOX process base the 28F010 builds on years of EPROM experience to yield the highest levels
of quality reliability and cost-effectiveness
Other brands and names are the property of their respective owners
Information in this document is provided in connection with Intel products Intel assumes no liability whatsoever including infringement of any patent or
copyright for sale and use of Intel products except as provided in Intel’s Terms and Conditions of Sale for such products Intel retains the right to make
changes to these specifications at any time without notice Microcomputer Products may have minor variations to this specification known as errata
COPYRIGHT INTEL CORPORATION 1995
November 1995
Order Number 290207-010



Intel Corporation
Intel Corporation

E28F010-65 Datasheet Preview

E28F010-65 Datasheet

1024K (128K x 8) CMOS FLASH MEMORY

No Preview Available !

E28F010-65 pdf
28F010
Symbol
A0 – A16
DQ0 – DQ7
CE
OE
WE
VPP
VCC
VSS
NC
Type
INPUT
INPUT OUTPUT
INPUT
INPUT
INPUT
Figure 1 28F010 Block Diagram
290207 – 1
Table 1 Pin Description
Name and Function
ADDRESS INPUTS for memory addresses Addresses are internally
latched during a write cycle
DATA INPUT OUTPUT Inputs data during memory write cycles
outputs data during memory read cycles The data pins are active high
and float to tri-state OFF when the chip is deselected or the outputs
are disabled Data is internally latched during a write cycle
CHIP ENABLE Activates the device’s control logic input buffers
decoders and sense amplifiers CE is active low CE high
deselects the memory device and reduces power consumption to
standby levels
OUTPUT ENABLE Gates the devices output through the data buffers
during a read cycle OE is active low
WRITE ENABLE Controls writes to the control register and the array
Write enable is active low Addresses are latched on the falling edge
and data is latched on the rising edge of the WE pulse
Note With VPP s 6 5V memory contents cannot be altered
ERASE PROGRAM POWER SUPPLY for writing the command
register erasing the entire array or programming bytes in the array
DEVICE POWER SUPPLY (5V g10%)
GROUND
NO INTERNAL CONNECTION to device Pin may be driven or left
floating
2


Part Number E28F010-65
Description 1024K (128K x 8) CMOS FLASH MEMORY
Maker Intel Corporation
Total Page 30 Pages
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