IDT723611 Datasheet | Integrated Device Technology

FEATURES : - Free-running CLKA and CLKB may be asynchronous or coincident (permits simultaneous reading and writing of data on a single clock edge) - 64 x 36 storage capacity - Synchronous data buffering from Port A to Port B - Mailbox bypass register in each direction - Programmable Almost-Full (AF) and Almost-Empty (AE) flags - Microprocessor Interface Control Logic - Full Flag (FF) and Almost-Full (AF) flags synchronized by CLKA - Empty Flag (EF) and Almost-Empty (AE) flags synchronized by CLKB - Passive parity checking on each Port - Parity Generation can be selected for each Port - Supports clock frequencies up to 67MHz - Fast access times of 10ns - Available in 132-pin Plastic Quad Flatpack (PQF) or space-saving 120-pin Thin Quad Flatpack (PF) - Low-power advanced CMOS technology - Industrial temperature range (-40o C to +85o C) is available, tested to military elecrical specifications DESCRIPTION : The IDT723611 is a monolithic, high-speed, low-power, CMOS Synchronous (clocked) FIFO memory which supports clock frequencies up to 67MHz and has read access times as fast as 10ns. The 64 x 36 dual-port FIFO buffers data from Port A to Port B. The FIFO has flags to indicate empty and full conditions, and two programmable flags, Almost-Full (AF) and Almost-Empty (AE), to indicate when a selected number of words is stored in memory. munication between each port can take place through two 36-bit mailbox registers. Each FUNCTIONAL BLOCK DIAGRAM CLKA W/RA ENA MBA Port-A Control Logic Parity Gen/Check Parity Generation MBF1 PEFB ODD/ Mail 1 Register Input Register Reset Logic EVEN 64 x 36 SRAM Output Register - 36 A0 - A35 Write Pointer Read Pointer B0 -...