| Description | The IDT71V546 is a 3.3V high-speed 4,718,592-bit (4.5 Megabit) synchronous SRAM organized as 128K x 36 bits. It is designed to eliminate dead bus cycles when turning the bus around between reads and writes, or writes and reads. Thus it has been given the name ZBTTM, or Zero Bus Turn-around. Address and control signals are applied to the SRAM during one Pin Description Summary A0 - A16 CE1, CE2, C... |
| Features |
128K x 36 memory configuration, pipelined outputs Supports high performance system speed - 133 MHz (4.2 ns Clock-to-Data Access) ZBTTM Feature - No dead cycles between write and read cycles Internally synchronized registered outputs eliminate the need to control OE Single R/W (READ/WRITE) control pin Positive clock-edge triggered address, data, and...
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| Datasheet |
 IDT71V546 Datasheet - 178.20KB |
