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Integrated Device Technology Electronic Components Datasheet

ICS87421I Datasheet

DIFFERENTIAL-TO-LVDS CLOCK GENERATOR

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÷1/÷2 DIFFERENTIAL-TO-LVDS
CLOCK GENERATOR
GENERAL DESCRIPTION
The ICS87421I is a high performance ÷1/÷2
ICS Differential-to-LVDS Clock Generator and a mem-
HiPerClockS™ ber of the HiPerClockS™ family of High Perfor-
mance Clock Solutions from IDT. The CLK, nCLK
pair can accept most standard differential input
levels. The ICS87421I is characterized to operate from a 3.3V
power supply. Guaranteed part-to-part skew characteristics
make the ICS87421I ideal for those clock distribution applica-
tions demanding well defined performance and repeatability.
ICS87421I
FEATURES
• One differential LVDS output
• One differential CLK, nCLK input pair
• CLK, nCLK pair can accept the following differential input
levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL
• Maximum clock input frequency: 1GHz
• Translates any single ended input signal (LVCMOS, LVTTL,
GTL) to LVDS levels with resistor bias on nCLK input
• Part-to-part skew: 500ps (maximum)
• Propagation delay: 1.7ns (maximum)
• Additive phase jitter, RMS @ 155.52MHz: 0.17ps (typical)
• Full 3.3V operating supply
• -40°C to 85°C ambient operating temperature
• Available in both standard (RoHS 5) and lead-free (RoHS 6)
packages
BLOCK DIAGRAM
CLK
nCLK
MR
÷1 0
R ÷2 1
F_SEL
Q
nQ
PIN ASSIGNMENT
CLK
nCLK
MR
F_SEL
1
2
3
4
8 VDD
7Q
6 nQ
5 GND
ICS87421I
8-Lead SOIC
3.90mm x 4.90mm x 1.37mm package body
M Package
Top View
IDT/ ICSLVDS CLOCK GENERATOR
1 ICS87421AMI REV. A OCTOBER 3, 2007


Integrated Device Technology Electronic Components Datasheet

ICS87421I Datasheet

DIFFERENTIAL-TO-LVDS CLOCK GENERATOR

No Preview Available !

ICS87421I pdf
ICS87421I
÷1/÷2 DIFFERENTIAL-TO-LVDS CLOCK GENERATOR
www.DataSheet4U.com
TABLE 1. PIN DESCRIPTIONS
Number
Name
Type
Description
1 CLK Input Pulldown Non-inverting differential clock input.
2
nCLK
Input
Pullup Inverting differential clock input.
Active High Master Reset. When logic HIGH, the internal dividers are
3
MR
Input
Pulldown
reset causing the true output (Q) to go low and the inverted output
(nQ) to go high. When logic LOW, the internal dividers and the output
are enabled. LVCMOS / LVTTL interface levels. See Table 3.
4
F_SEL
Input
Pulldown
Selects divider value for Q, nQ outputs as described in Table 3.
LVCMOS / LVTTL interface levels.
5
GND
Power
Power supply ground.
6, 7
Q, nQ
Output
Differential output pair. LVDS interface levels.
8 VDD Power
Positive supply pin.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol
CIN
RPULLUP
RPULLDOWN
Parameter
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
Test Conditions
Minimum
Typical
4
51
51
Maximum
Units
pF
kΩ
kΩ
TABLE 3. FUNCTION TABLE
MR F_SEL
Divide Value
1 X Reset: Q output low, nQ output high
00
÷1
01
÷2
CLK
MR
Q
FIGURE 1A. ÷1 CONFIGURATION TIMING DIAGRAM
FIGURE 1B. ÷2 CONFIGURATION TIMING DIAGRAM
IDT/ ICSLVDS CLOCK GENERATOR
2
ICS87421AMI REV. A OCTOBER 3, 2007


Part Number ICS87421I
Description DIFFERENTIAL-TO-LVDS CLOCK GENERATOR
Maker Integrated Device Technology
Total Page 14 Pages
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