http://www.www.datasheet4u.com

900,000+ Datasheet PDF Search and Download

Datasheet4U offers most rated semiconductors datasheets pdf




Integrated Device Technology Electronic Components Datasheet

ICS854S204I Datasheet

LVPECL FANOUT BUFFER

No Preview Available !

ICS854S204I pdf
LOW SKEW, DUAL, PROGRAMMABLE 1-TO-2 DIFFERENTIAL-
TO-LVDS, LVPECL FANOUT BUFFER
ICS854S204I
GENERAL DESCRIPTION
The ICS854S204I is a low skew, high performance
ICS dual, programmable 1-to-2 Differential-to-LVDS,
HiPerClockS™ LVPECL Fanout Buffer and a member of t h e
HiPerClock S™ family of High Performance Clock
Solutions from IDT. The PCLKx, nPCLKx pairs can
accept most standard differential input levels. With the selection of
SEL_OUT signal, outputs can be selected be to either LVDS or
LVPECL levels. The ICS854S204I is characterized to operate
from either a 2.5V or a 3.3V power supply. Guaranteed out-
put and bank skew characteristics make the ICS854S204I
wwidwe.aDlaftoarSthheoeste4Uc.cloocmk distribution applications demanding well
defined performance and repeatability.
FEATURES
Two programmable differential LVDS or LVPECL output banks
Two differential clock input pairs
PCLKx, nPCLKx pairs can accept the following differential
input levels: LVDS, LVPECL, SSTL, CML
Maximum output frequency: 3GHz
Translates any single ended input signal to LVDS levels
with resistor bias on nPCLKx inputs
Output skew: 15ps (maximum)
Bank skew: 15ps (maximum)
Propagation delay: 500ps (maximum)
Additive phase jitter, RMS: 0.15ps (typical)
Full 3.3V or 2.5V power supply
POWER SUPPLY CONFIGURATION TABLE
-40°C to 85°C ambient operating temperature
3.3V Operation
2.5V Operation
VDD = 3.3V
VTAP = nc
V = 2.5V
DD
VTAP = 2.5V
Available in lead-free (RoHS 6) package
SEL_OUT FUNCTION TABLE
SEL_OUT
0
1
Output Level
LVDS
LVPECL
BLOCK DIAGRAM
V
TAP
SEL_OUT Pulldown
PCLKA Pulldown
nPCLKA Pullup
PCLKB Pulldown
nPCLKB Pullup
QA0
nQA0
QA1
nQA1
QB0
nQB0
QB1
nQB1
PIN ASSIGNMENT
PCLKA
nPCLKA
QA0
nQA0
QA1
nQA1
VTAP
GND
1
2
3
4
5
6
7
8
16 nPCLKB
15 PCLKB
14 QB0
13 nQB0
12 QB1
11 nQB1
10 VDD
9 SEL_OUT
ICS854S204I
16-Lead TSSOP
4.4mm x 5.0mm x 0.925mm package body
G Package
Top View
IDT/ ICSLVDS, LVPECL FANOUT BUFFER
1
ICS854S204BGI REV. A JUNE 4, 2008


Integrated Device Technology Electronic Components Datasheet

ICS854S204I Datasheet

LVPECL FANOUT BUFFER

No Preview Available !

ICS854S204I pdf
ICS854S204I
LOW SKEW, DUAL, 1-TO-2 DIFFERENTIAL-TO-LVDS, LVPECL FANOUT BUFFER
TABLE 1. PIN DESCRIPTIONS
Number Name
Type
Description
1
PCLKA
Input Pulldown Non-inverting differential clock input.
2 nPCLKA Input Pullup Inverting differential clock input.
3, 4 QA0, nQA0 Output
Differential output pair. LVDS or LVPECL interface levels.
5, 6 QA1, nQA1 Output
Differential output pair. LVDS or LVPECL interface levels.
7 V Power
TAP
Power supply pin. Tie to VDD for 2.5V operation.
For 3.3V operation, do not connect.
8
GND
Power
Power supply ground.
9 SEL_OUT Input Pulldown Selects between LVDS or LVPECL outputs.
10 VDD
11, 12 nQB1, QB1
www.DataSheet4U.com
13, 14 nQB0, QB0
Power
Output
Output
Power supply pin.
Differential output pair. LVDS or LVPECL interface levels.
Differential output pair. LVDS or LVPECL interface levels.
15 PCLKB Input Pulldown Non-inverting differential clock input.
16 nPCLKB Input Pullup Inverting differential clock input.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol
CIN
RPULLUP
RPULLDOWN
Parameter
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
Test Conditions
Minimum
Typical
1
51
51
Maximum
Units
pF
kΩ
kΩ
TABLE 3. CLOCK INPUT FUNCTION TABLE
Inputs
PCLKA or
PCLKB
nPCLKA or
nPCLKB
Outputs
QA0, QA1,
QB0, QB1
nQA0, nQA1,
nQB0, nQB1
Input to Output Mode
Polarity
0
1
LOW
HIGH
Differential to Differential Non Inverting
1
0
HIGH
LOW
Differential to Differential Non Inverting
0
Biased; NOTE 1
LOW
HIGH
Single Ended to Differential Non Inverting
1
Biased; NOTE 1
HIGH
LOW
Single Ended to Differential Non Inverting
Biased; NOTE 1
0
HIGH
LOW
Single Ended to Differential
Inverting
Biased; NOTE 1
1
LOW
HIGH
Single Ended to Differential
Inverting
NOTE 1: Please refer to the Application Information, "Wiring the Differential Input to Accept Single Ended Levels".
IDT/ ICSLVDS, LVPECL FANOUT BUFFER
2
ICS854S204BGI REV. A JUNE 4, 2008


Part Number ICS854S204I
Description LVPECL FANOUT BUFFER
Maker Integrated Device Technology
Total Page 19 Pages
PDF Download
ICS854S204I pdf
Download PDF File
ICS854S204I pdf
View for Mobile



Buy Electronic Components




Related Datasheet

1 ICS854S204I LVPECL FANOUT BUFFER Integrated Device Technology
Integrated Device Technology
ICS854S204I pdf






Part Number Start With

0    1    2    3    4    5    6    7    8    9    A    B    C    D    E    F    G    H    I    J    K    L    M    N    O    P    Q    R    S    T    U    V    W    X    Y    Z

site map

webmaste! click here

contact us

Buy Components