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ICS854S054I Datasheet

4:1 Differential-to-LVDS Clock Multiplexer

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ICS854S054I pdf
4:1 Differential-to-LVDS Clock Multiplexer
ICS854S054I
DATA SHEET
General Description
The ICS854S054I is a 4:1 Differential-to-LVDS Clock Multiplexer
which can operate up to 2.5GHz. The ICS854S054I has 4 selectable
differential clock inputs. The PCLK, nPCLK input pairs can accept
LVPECL, LVDS or CML levels. The fully differential architecture and
low propagation delay make it ideal for use in clock distribution
circuits. The select pins have internal pulldown resistors. The SEL1
pin is the most significant bit and the binary number applied to the
select pins will select the same numbered data input (i.e., 00 selects
PCLK0, nPCLK0).
Features
High speed 4:1 differential multiplexer
One differential LVDS output pair
Four selectable differential PCLK, nPCLK input pairs
PCLKx, nPCLKx pairs can accept the following differential
input levels: LVPECL, LVDS, CML
Maximum output frequency: 2.5GHz
Translates any single ended input signal to LVDS levels with
resistor bias on nPCLKx input
Additive phase jitter, RMS: 0.147ps (typical)
Part-to-part skew: 300ps (maximum)
Propagation delay: 700ps (maximum)
Supply voltage range: 3.135V to 3.465V
-40°C to 85°C ambient operating temperature
Available in lead-free (RoHS 6) package
Block Diagram
PCLK0 Pulldown
nPCLK0 Pullup/Pulldown
PCLK1 Pulldown
nPCLK1 Pullup/Pulldown
PCLK2 Pulldown
nPCLK2 Pullup/Pulldown
PCLK3 Pulldown
nPCLK3 Pullup/Pulldown
00 (default)
01
10
11
SEL1 Pulldown
SEL0 Pulldown
ICS854S054AGI REVISION A SEPTEMBER 28, 2012
Pin Assignment
PCLK0
nPCLK0
PCLK1
nPCLK1
VDD
SEL0
SEL1
GND
1
2
3
4
5
6
7
8
16 VDD
15 Q
14 nQ
13 GND
12 nPCLK3
11 PCLK3
10 nPCLK2
9 PCLK2
ICS854S054I
16-Lead TSSOP
Q 5.0mm x 4.4mm x 0.92mm package body
nQ G Package
Top View
1 ©2012 Integrated Device Technology, Inc.


Integrated Device Technology Electronic Components Datasheet

ICS854S054I Datasheet

4:1 Differential-to-LVDS Clock Multiplexer

No Preview Available !

ICS854S054I pdf
ICS854S054I Data Sheet
4:1, DIFFERENTIAL-TO-LVDS CLOCK MULTIPLEXER
Table 1. Pin Descriptions
Number
1
2
3
4
5, 16
6, 7
9
10
11
12
8, 13
14, 15
Name
PCLK0
nPCLK0
PCLK1
nPCLK1
VDD
SEL0, SEL1
PCLK2
nPCLK2
PCLK3
nPCLK3
GND
nQ, Q
Type
Input
Pulldown
Input
Pullup/
Pulldown
Input
Pulldown
Input
Pullup/
Pulldown
Power
Input
Pulldown
Input
Pulldown
Input
Pullup/
Pulldown
Input
Pulldown
Input
Pullup/
Pulldown
Power
Output
Description
Non-inverting differential clock input.
Inverting differential clock input. VDD/2 default when left floating.
Non-inverting differential clock input.
Inverting differential clock input. VDD/2 default when left floating.
Positive supply pins.
Clock select input pins. LVCMOS/LVTTL interface levels.
Non-inverting differential clock input.
Inverting differential clock input. VDD/2 default when left floating.
Non-inverting differential clock input.
Inverting differential clock input. VDD/2 default when left floating.
Power supply ground.
Differential output pair. LVDS interface levels.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
Symbol
CIN
RPULLDOWN
RVDD/2
Parameter
Input Capacitance
Pulldown Resistor
RPullup/Pulldown Resistor
Test Conditions
Table 3. Clock Input Function Table
SEL1
0
0
1
1
Inputs
SEL0
0
1
0
1
Outputs
Q nQ
PCLK0
nPCLK0
PCLK1
nPCLK1
PCLK2
nPCLK2
PCLK3
nPCLK3
Minimum
Typical
2
75
50
Maximum
Units
pF
k
k
ICS854S054AGI REVISION A SEPTEMBER 28, 2012
2
©2012 Integrated Device Technology, Inc.


Part Number ICS854S054I
Description 4:1 Differential-to-LVDS Clock Multiplexer
Maker Integrated Device Technology
Total Page 14 Pages
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