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ICS8543I Datasheet

Differential-to-LVDS Fanout Buffer

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ICS8543I pdf
Low Skew, 1-to-4,
Differential-to-LVDS Fanout Buffer
ICS8543I
DATA SHEET
General Description
The ICS8543I is a low skew, high performance 1-to-4 Differen-
tial-to-LVDS Clock Fanout Buffer. Utilizing Low Voltage Differential
Signaling (LVDS) the ICS8543I provides a low power, low noise, so-
lution for distributing clock signals over controlled impedances of
100. The ICS8543I has two selectable clock inputs. The CLK,
nCLK pair can accept most standard differential input levels. The
PCLK, nPCLK pair can accept LVPECL, CML, or SSTL input levels.
The clock enable is internally synchronized to eliminate runt pulses
on the outputs during asynchronous assertion/deassertion of the
clock enable pin.
Guaranteed output and part-to-part skew characteristics make the
ICS8543I ideal for those applications demanding well defined perfor-
mance and repeatability.
Features
Four differential LVDS output pairs
Selectable differential CLK/nCLK or LVPECL clock inputs
CLK/nCLK pair can accept the following differential input levels:
LVPECL, LVDS, LVHSTL, SSTL, HCSL
PCLK/nPCLK pair can accept the following differential input
levels: LVPECL, CML, SSTL
Maximum output frequency: 650MHz
Translates any single-ended input signals to LVDS levels with
resistor bias on nCLK input
Additive phase Jitter, RMS: 0.164ps (typical)
Output skew: 40ps (maximum)
Part-to-part skew: 600ps (maximum)
Propagation delay: 2.6ns (maximum)
Full 3.3Vsupply mode
-40°C to 85°C ambient operating temperature
Available in lead-free packages
Block Diagram
CLK_EN Pullup
CLK Pulldown
nCLK Pullup
PCLK Pulldown
nPCLK Pullup
CLK_SEL Pulldown
00
1
1
D
Q
LE
OE Pullup
Pin Assignment
Q0
nQ0
Q1
nQ1
Q2
nQ2
Q3
nQ3
GND
CLK_EN
CLK_SEL
CLK
nCLK
PCLK
nPCLK
OE
GND
VDD
1
2
3
4
5
6
7
8
9
10
20 Q0
19 nQ0
18 VDD
17 Q1
16 nQ1
15 Q2
14 nQ2
13 GND
12 Q3
11 nQ3
ICS8543I
20-Lead TSSOP
6.5mm x 4.4mm x 0.925mm
package body
G Package
Top View
ICS8543BGI REVISION E NOVEMBER 15, 2012
1
©2012 Integrated Device Technology, Inc.


Integrated Device Technology Electronic Components Datasheet

ICS8543I Datasheet

Differential-to-LVDS Fanout Buffer

No Preview Available !

ICS8543I pdf
ICS8543I Data Sheet
LOW SKEW, 1-to-4, DIFFERENTIAL-TO-LVDS FANOUT BUFFER
Table 1. Pin Descriptions
Number
1, 9, 13
2
3
Name
GND
CLK_EN
CLK_SEL
Type
Power
Input
Pullup
Input
Pulldown
Description
Power supply ground.
Synchronizing clock enable. When HIGH, clock outputs follows clock input.
When LOW, Qx outputs are forced low, nQx outputs are forced high.
LVCMOS / LVTTL interface levels.
Clock select input. When HIGH, selects PCLK/nPCLK inputs.
When LOW, selects CLK/nCLK inputs. LVCMOS / LVTTL interface levels.
4
5
6
7
8
10, 18
11, 12
14, 15
16, 17
19, 20
CLK
nCLK
PCLK
nPCLK
OE
VDD
nQ3, Q3
nQ2, Q2
nQ1, Q1
nQ0, Q0
Input
Input
Input
Input
Input
Power
Output
Output
Output
Output
Pulldown
Pullup
Pulldown
Pullup
Pullup
Non-inverting differential clock input.
Inverting differential clock input.
Non-inverting differential LVPECL clock input.
Inverting differential LVPECL clock input.
Output enable. Controls enabling and disabling of outputs Q0/nQ0 through
Q3/nQ3. LVCMOS/LVTTL interface levels.
Positive supply pins.
Differential output pair. LVDS interface levels.
Differential output pair. LVDS interface levels.
Differential output pair. LVDS interface levels.
Differential output pair. LVDS interface levels.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
Symbol
CIN
RPULLUP
RPULLDOWN
Parameter
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
Test Conditions
Minimum
Typical
4
51
51
Maximum
Units
pF
k
k
ICS8543BGI REVISION E NOVEMBER 15, 2012
2
©2012 Integrated Device Technology, Inc.


Part Number ICS8543I
Description Differential-to-LVDS Fanout Buffer
Maker Integrated Device Technology
Total Page 17 Pages
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