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ICS8530-01 Datasheet

Differential-to-3.3V LVPECL Fanout Buffer

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ICS8530-01 pdf
Low Skew, 1-to16, Differential-to-3.3V
LVPECL Fanout Buffer
ICS8530-01
DATA SHEET
General Description
The ICS8530-01 is a low skew, 1-to-16 Differential-to-3.3V LVPECL
Fanout Buffer. The CLK, nCLK pair can accept most standard
differential input levels. The high gain differential amplifier accepts
peak-to-peak input voltages as small as 150mV as long as the
common mode voltage is within the specified minimum and
maximum range.
Guaranteed output and part-to-part skew characteristics make the
ICS8530-01 ideal for those clock distribution applications
demanding well defined performance and repeatability.
Features
Sixteen differential 3.3V LVPECL outputs
CLK, nCLK input pair
CLK, nCLK pair can accept the following differential input
levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL
Maximum output frequency: 500MHz
Translates any single-ended input signal to 3.3V LVPECL levels
with a resistor bias on nCLK input
Output skew: 75ps (maximum)
Part-to-part skew: 305ps (maximum)
Additive phase jitter, RMS: 0.03ps (typical)
Full 3.3V supply voltage
0°C to 70°C ambient operating temperature
Available in both standard (RoHS 5) and lead-free (RoHS 6)
packages
Block Diagram
CLK Pulldown
nCLK Pullup
Q0
nQ0
Q1
nQ1
Q2
nQ2
Q3
nQ3
Q4
nQ4
Q5
nQ5
Q6
nQ6
Q7
nQ7
Q15
nQ15
Q14
nQ14
Q13
nQ13
Q12
nQ12
Q11
nQ11
Q10
nQ10
Q9
nQ9
Q8
nQ8
ICS8530FY-01 REVISION G NOVEMBER 15, 2012
Pin Assignment
VCCO
Q11
nQ11
Q10
nQ10
VEE
Q9
nQ9
Q8
nQ8
VCCO
VCC
48 47 46 45 44 43 42 41 40 39 38 37
1 36
2 35
3 34
4 33
5 32
6 31
7 30
8 29
9 28
10 27
11 26
12 25
13 14 15 16 17 18 19 20 21 22 23 24
CLK
VCCO
nQ0
Q0
nQ1
Q1
VEE
nQ2
Q2
nQ3
Q3
VCCO
ICS8530-01
48-Lead LQFP
7mm x 7mm x 1.4mm package body
Y Package
Top View
1 ©2012 Integrated Device Technology, Inc.


Integrated Device Technology Electronic Components Datasheet

ICS8530-01 Datasheet

Differential-to-3.3V LVPECL Fanout Buffer

No Preview Available !

ICS8530-01 pdf
ICS8530-01 Data Sheet
LOW SKEW, 1-TO-16, DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER
Table 1. Pin Descriptions
Number
1, 11, 14, 24, 25, 35, 38, 48
2, 3
4, 5
6, 19, 30, 43
7, 8
9, 10
12, 13
15, 16
17, 18
20, 21
22, 23
26, 27
28, 29
31, 32
33, 34
36
37
39, 40
41, 42
44, 45
46, 47
Name
VCCO
Q11, nQ11
Q10, nQ10
VEE
Q9, nQ9
Q8, nQ8
VCC
Q7, nQ7
Q6, nQ6
Q5, nQ5
Q4, nQ4
Q3, nQ3
Q2, nQ2
Q1, nQ1
Q0, nQ0
CLK
nCLK
Q15, nQ15
Q14, nQ14
Q13, nQ13
Q12, nQ12
Type
Power
Output
Output
Power
Output
Output
Power
Output
Output
Output
Output
Output
Output
Output
Output
Input
Pulldown
Input
Pullup
Output
Output
Output
Output
Description
Output supply pins.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Negative supply pins.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Power supply pins.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Non-inverting differential clock input.
Inverting differential clock input.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
Symbol
Parameter
CIN
RPULLUP
RPULLDOWN
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
Test Conditions
Minimum
Typical
3
51
51
Maximum
Units
pF
k
k
ICS8530FY-01 REVISION G NOVEMBER 15, 2012
2
©2012 Integrated Device Technology, Inc.


Part Number ICS8530-01
Description Differential-to-3.3V LVPECL Fanout Buffer
Maker Integrated Device Technology
Total Page 17 Pages
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