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Integrated Device Technology Electronic Components Datasheet

ICS85105I Datasheet

DIFFERENTIAL/LVCMOS-TO-0.7V HCSL FANOUT BUFFER

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ICS85105I pdf
LOW SKEW, 1-TO-5, DIFFERENTIAL/
LVCMOS-TO-0.7V HCSL FANOUT BUFFER
ICS85105I
GENERAL DESCRIPTION
The ICS85105I is a low skew, high performance 1-
ICS to-5 Differential-to-0.7V HCSL Fanout Buffer and
HiPerClockS™ a member of the HiPerClockS™ family of High
Perfor mance Clock Solutions from IDT. The
ICS85105I has two selectable clock inputs. The
CLK0, nCLK0 pair can accept most standard differential
input levels. The single-ended CLK1 can accept LVCMOS or
LVTTL input levels. The clock enable is internally synchronized
to eliminate runt clock pulses on the outputs during asynchro-
nous assertion/deassertion of the clock enable pin.
Guaranteed output and part-to-part skew characteristics make
the ICS85105I ideal for those applications demanding well
defined performance and repeatability.
FEATURES
Five 0.7V differential HCSL outputs
Selectable differential CLK0, nCLK0 or LVCMOS inputs
CLK0, nCLK0 pair can accept the following differential
input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL
CLK1 can accept the following input levels:
LVCMOS or LVTTL
Maximum output frequency: 500MHz
Translates any single-ended input signal to 3.3V
HCSL levels with resistor bias on nCLK input
Output skew: 100ps (maximum)
Part-to-part skew: 600ps (maximum)
Propagation delay: 3.2ns (maximuml)
Additive phase jitter, RMS: 0.24ps (typical)
3.3V operating supply
-40°C to 85°C ambient operating temperature
Available in both standard (RoHS 5) and lead-free (RoHS 6)
packages
BLOCK DIAGRAM
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CLK0 Pulldown
nCLK0 Pullup/Pulldown
0
CLK1 Pulldown
CLK_SEL Pulldown
1
IREF
D
Q
LE
PIN ASSIGNMENT
GND 1 20 Q0
CLK_EN 2 19 nQ0
CLK_SEL 3
CLK0 4
18 VDD
17 Q1
nCLK0 5 16 nQ1
Q0
nQ0
CLK1 6
Q4 7
15 Q2
14 nQ2
Q1
nQ4 8
13 VDD
nQ1 IREF 9 12 Q3
VDD 10 11 nQ3
Q2
nQ2 ICS85105I
Q3 20-Lead TSSOP
nQ3 6.5mm x 4.4mm x 0.925mm Package Body
G Package
Q4
nQ4
Top View
IDT/ ICS0.7V HCSL FANOUT BUFFER
1
ICS85105AGI REV. A JUNE 5, 2008


Integrated Device Technology Electronic Components Datasheet

ICS85105I Datasheet

DIFFERENTIAL/LVCMOS-TO-0.7V HCSL FANOUT BUFFER

No Preview Available !

ICS85105I pdf
ICS85105I
LOW SKEW, 1-TO-5, DIFFERENTIAL/LVCMOS-TO-0.7V HCSL FANOUT BUFFER
TABLE 1. PIN DESCRIPTIONS
Number
Name
Type
Description
1
GND
Power
Power supply ground.
Synchronizing clock enable. When HIGH, clock outputs follow clock input.
2 CLK_EN Input Pullup When LOW, Qx outputs are forced low, nQx outputs are forced high.
LVTTL / LVCMOS interface levels.
Clock select input. When HIGH, selects CLK1 input.
3 CLK_SEL Input Pulldown When LOW, selects CLK0, nCLK0 inputs.
LVTTL / LVCMOS interface levels.
4
CLK0
Input Pulldown Non-inverting differential clock input.
5
nCLK0
Input
Pullup/
Pulldown
Inverting differential clock input.
6
CLK1
Input Pulldown Single-ended clock input. LVTTL / LVCMOS interface levels.
7, 8 Q4, nQ4 Output
9
IREF
Input
Differential output pair. HCSL interface levels.
An external fixed precision resistor (475Ω) from this pin to ground provides
a reference current used for differential current-mode Qx/nQx outputs.
10, 13, 18
11, 12
VDD
nQ3, Q3
Power
Output
Positive supply pins.
Differential output pair. HCSL interface levels.
14, 15 nQ2, Q2 Output
Differential output pair. HCSL interface levels.
16, 17
nQ1, Q1 Output
Differential output pair. HCSL interface levels.
19, 20
nQ0, Q0 Output
Differential output pair. HCSL interface levels.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol
CIN
R
PULLUP
R
PULLDOWN
Parameter
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
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Test Conditions
Minimum
Typical
4
51
51
Maximum
Units
pF
kΩ
kΩ
IDT/ ICS0.7V HCSL FANOUT BUFFER
2
ICS85105AGI REV. A JUNE 5, 2008


Part Number ICS85105I
Description DIFFERENTIAL/LVCMOS-TO-0.7V HCSL FANOUT BUFFER
Maker Integrated Device Technology
Total Page 16 Pages
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