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Integrated Device Technology Electronic Components Datasheet

ICS841S02I Datasheet

PCI EXPRESS CLOCK GENERATOR

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PCI EXPRESS™ CLOCK GENERATOR
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PRELIMINARY
ICS841S02I
GENERAL DESCRIPTION
The ICS841S02I is a PLL-based clock generator
ICS specifically designed for PCI_Express™Clock
HiPerClockS™ Generation applications. This device generates a
100MHz HCSL clock. The device offers a HCSL
(Host Clock Signal Level) clock output from a clock
input reference of 25MHz. The input reference may be derived
from an external source or by the addition of a 25MHz crystal to
the on-chip crystal oscillator. An external reference may be applied
to the XTAL_IN pin with the XTAL_OUT pin left floating.
The device offers spread spectrum clock output for reduced EMI
applications. An I2C bus interface is used to enable or disable
spread spectrum operation as well as select either a down spread
value of -0.35% or -0.5%.
The ICS841S02I is available in both standard and lead-free
20-Lead TSSOP packages.
FEATURES
Two 0.7V current mode differential HCSL output pairs
Crystal oscillator interface, 25MHz
Output frequency: 100MHz
RMS period jitter: 3ps (maximum)
Output skew: 35ps (maximum)
Cycle-to-cyle jitter: 35ps (maximum)
I2C support with readback capabilities up to 400kHz
Spread Spectrum for electromagnetic interference (EMI)
reduction
3.3V operating supply mode
-40°C to 85°C ambient operating temperature
Available in both standard (RoHS 5) and lead-free (RoHS 6)
packages
BLOCK DIAGRAM
25MHz
XTAL_IN
OSC
XTAL_OUT
SDATA Pullup
SCLK Pullup
PLL
I2C
Logic
IREF
Divider
Network
SRCT[1:2]
SRCC[1:2]
PIN ASSIGNMENT
VSS_SRC
VDD_SRC
SRCT2
SRCC2
SRCT1
SRCC1
VSS_SRC
VDD_SRC
VSS_SRC
IREF
1
2
3
4
5
6
7
8
9
10
20 VDD_SRC
19 SDATA
18 SCLK
17 nc
16 XTAL_OUT
15 XTAL_IN
14 VDD_REF
13 VSS_REF
12 VDDA
11 VSSA
ICS841S02I
20-Lead TSSOP
6.5mm x 4.4mm x 0.92mm
package body
G Package
Top View
The Preliminary Information presented herein represents a product in pre-production. The noted characteristics are based on initial product characterization
and/or qualification. Integrated Device Technology, Incorporated (IDT) reserves the right to change any circuitry or specifications without notice.
IDT/ ICSPCI EXPRESS CLOCK GENERATOR
1
ICS841S02BGI REV. C NOVEMBER 1, 2007



Integrated Device Technology Electronic Components Datasheet

ICS841S02I Datasheet

PCI EXPRESS CLOCK GENERATOR

No Preview Available !

ICS841S02I pdf
ICS841S02I
PCI EXPRESS™ CLOCK GENERATOR
www.DPatRaSEhLeeItM4UIN.coAmRY
TABLE 1. PIN DESCRIPTIONS
Number
Name
Type
Description
1, 7, 9
2, 8, 20
3, 4
VSS_SRC
VDD_SRC
SRCT2, SRCC2
Power
Power
Output
Ground for core and SRC outputs.
Power supply for core and SRC outputs.
Differential output pair. HCSL interface levels.
5, 6 SRCT1, SRCC1 Output
Differential output pair. HCSL interface levels.
A fixed precision resistor (475W) from this pin to ground provides a
10
IREF
Input
reference current used for differential current-mode SRCCx, SRCTx
clock outputs.
11
12
13
14
15, 16
VSSA
VDDA
VSS_REF
VDD_REF
XTAL_IN, XTAL_OUT
Power
Power
Power
Power
Input
Analog ground pin.
Power supply for PLL.
Ground for crystal interface
Power supply for crystal interface.
Crystal oscillator interface. XTAL_IN is the input.
XTAL_OUT is the output.
17
nc
Unused
No connect.
SMBus compatible SCLK. This pin has an internal pullup resistor,
18
SCLK
Input Pullup but is in high impedance in powerdown mode.
LVCMOS/LVTTL interface levels.
19
SDATA
Input/
Output
SMBus compatible SDATA. This pin has an internal pullup resistor,
Pullup but is in high impedance in powerdown mode.
LVCMOS/LVTTL interface levels.
NOTE: Pullup refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol
C
IN
RPULLUP
COUT
LIN
Parameter
Input Capacitance
Input Pullup Resistor
Output Pin Capacitance
Pin Inductance
Test Conditions
Minimum
3
Typical
4
51
Maximum
5
7
Units
pF
kΩ
pF
nH
IDT/ ICSPCI EXPRESS CLOCK GENERATOR
2
ICS841S02BGI REV. C NOVEMBER 1, 2007



Integrated Device Technology Electronic Components Datasheet

ICS841S02I Datasheet

PCI EXPRESS CLOCK GENERATOR

No Preview Available !

ICS841S02I pdf
ICS841S02I
PCI EXPRESS™ CLOCK GENERATOR
www.DPatRaSEhLeeItM4UIN.coAmRY
SERIAL DATA INTERFACE
To enhance the flexibility and function of the clock synthesizer,
a two-signal serial interface is provided. Through the Serial Data
Interface, various device functions, such as individual clock
output buffers, can be individually enabled or disabled. The
registers associated with the Serial Data Interface initialize to
their default setting upon power-up, and therefore, use of this
interface is optional. Clock device register changes are nor-
mally made upon system initialization, if any are required. The
interface cannot be used during system operation for power
management functions.
DATA PROTOCOL
The clock driver serial protocol accepts byte write, byte read,
block write, and block read operations from the controller. For
block write/read operation, the bytes must be accessed in se-
quential order from lowest to highest byte (most significant bit
first) with the ability to stop after any complete byte has been
transferred. For byte write and byte read operations, the sys-
tem controller can access individually indexed bytes. The off-
set of the indexed byte is encoded in the command code, as
described in Table 3A.
The block write and block read protocol is outlined in Table 3B,
while Table 3C outlines the corresponding byte write and byte
read protocol. The slave receiver address is 11010010 (D2h).
TABLE 3A. COMMAND CODE DEFINITION
BIT Description
7 0 = Block read or block write operation, 1 = Byte read or byte write operation.
6:5 Chip select address, set to "00" to access device.
4:0
Byte offset for byte read or byte write operation. For block read or block write operations, these bits must be
"00000".
TABLE 3B. BLOCK READ AND BLOCK WRITE PROTOCOL
BIT
1
2:8
9
10
11:18
19
20:27
28
29:36
37
38:45
46
Description = Block Write
Start
Slave address - 7 bits
Write
Acknowledge from slave
Command Code - 8 bits
Acknowledge from slave
Byte Count - 8 bits
Acknowledge from slave
Data byte 1 - 8 bits
Acknowledge from slave
Data byte 2 - 8 bits
Acknowledge from slave
Data Byte/Slave Acknowledges
Data Byte N - 8 bits
Acknowledge from slave
Stop
BIT
1
2:8
9
10
11:18
19
20
21:27
28
29
30:37
38
39:46
47
48:55
56
Description = Block Read
Start
Slave address - 7 bits
Write
Acknowledge from slave
Command Code - 8 bits
Acknowledge from slave
Repeat start
Slave address - 7 bits
Read = 1
Acknowledge from slave
Byte Count from slave - 8 bits
Acknowledge
Data Byte 1 from slave - 8 bits
Acknowledge
Data Byte 2 from slave - 8 bits
Acknowledge
Data Bytes from Slave / Acknowledges
Data Byte N from slave - 8 bits
Not Acknowledge
IDT/ ICSPCI EXPRESS CLOCK GENERATOR
3
ICS841S02BGI REV. C NOVEMBER 1, 2007




Part Number ICS841S02I
Description PCI EXPRESS CLOCK GENERATOR
Maker Integrated Device Technology
Total Page 17 Pages
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