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Integrated Device Technology Electronic Components Datasheet

ICS841664I Datasheet

FEMTOCLOCK CRYSTAL-TO-HCSL CLOCK GENERATOR

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PRELIMINARY
FEMTOCLOCK™ CRYSTAL-TO-HCSL
CLOCK GENERATOR
GENERAL DESCRIPTION
The ICS841664I is an optimized sRIO clock
ICS generator and member of the HiPerClocks™ family
HiPerClockS™ of high-perfor mance clock solutions from IDT.
The device uses a 25MHz parallel crystal to gen-
erate 125MHz and 156.25MHz clock signals,
replacing solutions requiring multiple oscillator and fanout buffer
solutions. The device has excellent phase jitter (< 1ps rms) suit-
able to clock components requiring precise and low-jitter sRIO
clock signals. Designed for telecom, networking and industrial
applications, the ICS841664I can also drive the high-speed
sRIO SerDes clock inputs of communication processors, DSPs,
switches and bridges.
ICS841664I
FEATURES
• Four differential HCSL clock outputs: configurable for sRIO
(125MHz or 156.25MHz) clock signals
One REF_OUT LVCMOS/LVTTL clock output
• Selectable crystal oscillator interface, 25MHz, 18pF parallel
resonant crystal or LVCMOS/LVTTL single-ended reference
clock input
• Supports the following output frequencies:
125MHz or 156.25MHz
• VCO: 625MHz
• PLL bypass and output enable
• RMS phase jitter, using a 25MHz crystal (1.875MHz - 20MHz):
0.35ps (typical) @ 125MHz
• Full 3.3V power supply mode
• -40°C to 85°C ambient operating temperature
• Available in both standard (RoHS 5) and lead-free (RoHS 6)
packages
BLOCK DIAGRAM
XTAL_IN
XTAL_OUT
OSC
REF_IN Pulldown
0
1
REF_SEL Pulldown
IREF
BYPASS Pulldown
FSEL[0:1] Pulldown
MR/nOE Pulldown
1
FemtoClock
PLL 0 ÷NA
VCO = 625MHz
M = ÷25
÷NB
nREF_OE Pullup
QA0
nQA0
QA1
nQA1
QB0
nQB0
QB1
nQB1
REF_OUT
PIN ASSIGNMENT
VDD
REF_OUT
GND
QA0
nQA0
VDDOA
GND
QA1
nQA1
nREF_OE
BYPASS
REF_IN
REF_SEL
VDDA
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28 IREF
27 FSEL0
26 FSEL1
25 QB0
24 nQB0
23 VDDOB
22 GND
21 QB1
20 nQB1
19 MR/nOE
18 VDD
17 XTAL_IN
16 XTAL_OUT
15 GND
ICS841664I
28-Lead TSSOP
6.1mm x 9.7mm x 0.925mm
package body
G Package
Top View
The Preliminary Information presented herein represents a product in pre-production. The noted characteristics are based on initial product characterization
and/or qualification. Integrated Device Technology, Incorporated (IDT) reserves the right to change any circuitry or specifications without notice.
IDT/ ICSHCSL CLOCK GENERATOR
1 ICS841664AGI REV. A JANUARY 30, 2009


Integrated Device Technology Electronic Components Datasheet

ICS841664I Datasheet

FEMTOCLOCK CRYSTAL-TO-HCSL CLOCK GENERATOR

No Preview Available !

ICS841664I pdf
ICS841664I
FEMTOCLOCK™ CRYSTAL-TO-HCSL CLOCK GENERATOR
www.DPatRaSEhLeeItM4UIN.coAmRY
TABLE 1. PIN DESCRIPTIONS
Number
Name
Type
Description
1, 18
2
VDD Power
REF_OUT Output
Core supply pins.
LVCMOS/LVTTL reference frequency clock output.
3, 7, 15, 22
GND
Power
4, 5,
8, 9
QA0, nQA0,
QA1, nQA1
Ouput
Power supply ground.
Differential Bank A output pairs. HCSL interface levels.
6
VDDOA
Power
Output supply pin for Bank A outputs.
10
nREF_OE Input
Pullup
Active low REF_OUT enable/disable. See Table 3E.
LVCMOS/LVTTL interface levels.
11
BYPASS
Input
Pulldown
Selects PLL operation/PLL bypass operation.
See Table 3C. LVCMOS/LVTTL interface levels.
12 REF_IN Input Pulldown LVCMOS/LVTTL PLL reference clock input.
13
REF_SEL
Input
Pulldown
Reference select. Selects the input reference source.
See Table 3B. LVCMOS/LVTTL interface levels.
14
16, 17
19
20, 21
24, 25
VDDA
XTAL_OUT,
XTAL_IN
MR/nOE
nQB1, QB1
nQB0, QB0
Power
Input
Input
Output
Pulldown
Analog supply pin.
Parallel resonant crystal interface. XTAL_OUT is the output,
XTAL_IN is the input. (PLL reference.)
Active HIGH master reset. Active LOW output enable. When logic HIGH,
the internal dividers are reset and the outputs are in high impedance
(HiZ). When logic LOW, the internal dividers and the outputs are enabled.
See Table 3D. LVCMOS/LVTTL interface levels.
Differential Bank B output pairs. HCSL interface levels.
23
26, 27
VDDOB
FSEL1,
FSEL0
Power
Output supply pin for Bank B outputs.
Input Pulldown Output frequency select pins. LVCMOS/LVTTL interface levels.
28
IREF
Output
HCSL current reference resistor output. A fixed precision resistor (475Ω)
from this pin to ground provides a reference current used for differential
current-mode QXx/nQXx clock outputs.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol
C
IN
CPD
RPULLUP
RPULLDOWN
Parameter
Input Capacitance
Power Dissipation
Capacitance
Input PullupResistor
Input Pulldown Resistor
Test Conditions
VDD, VDDOA, VDDOB = 3.465V
Minimum
Typical
4
18
51
51
Maximum Units
pF
pF
kΩ
kΩ
IDT/ ICSHCSL CLOCK GENERATOR
2 ICS841664AGI REV. A JANUARY 30, 2009


Part Number ICS841664I
Description FEMTOCLOCK CRYSTAL-TO-HCSL CLOCK GENERATOR
Maker Integrated Device Technology
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