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Integrated Device Technology Electronic Components Datasheet

ICS810251I Datasheet

VCXO and Synchronous Ethernet Jitter Attenuator

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ICS810251I pdf
VCXO and Synchronous Ethernet
Jitter Attenuator
ICS810251I
DATA SHEET
General Description
The ICS810251I is a high performance, low jitter/low phase noise
VCXO. The ICS810251i uses a low frequency and low cost pullable
crystal to achieve jitter attenuation for synchronous Ethernet
applications. The ICS810251I can take an input of either 25MHz or
125MHz and produce a single LVCMOS output of 25MHz.
The device is packaged in a small 16 lead TSSOP package and is
ideal for use on space constrained boards typically encountered in
most synchronous ethernet applications.
Applications
Synchronous Ethernet v0.39a
End equipment compliant with Std IEEE 802.039a
Features
One single-ended output (LVCMOS or LVTTL levels),
output Impedance: 15
Phase jitter attenuation by the VCXO-PLL using a 25MHz pullable
external crystal (XTAL)
Input frequencies: 25MHz or 125MHz
Output frequency: 25MHz
PLL loop bandwidth adjustable by external components
25MHz or 125MHz auto input frequency detect
Full 3.3V or 2.5V supply voltage
-40°C to 85°C ambient operating temperature
Available in lead-free (RoHS 6) package
Block Diagram
(External loop
filter inputs.)
LF1 LF0
25MHz
OE
CLK_IN
(25MHz or 125MHz
input frequency auto
detect)
Pre-
divider
(÷1 or ÷5)
PFD CP VCXO
VCXO-PLL
1
0
Q
25MHz
Pin Assignment
PLL_SEL
GND
Reserved
Q
VDDO
OE
VDDA
V DD
1
2
3
4
5
6
7
8
16 CLK_IN
15 V DD
14 LF1
13 LF0
12 GND
11 XTAL_IN
10 XTAL_OUT
9 GND
ICS810251I
16-Lead TSSOP
4.4mm x 5.0mm x 0.925mm
package body
G Package
Top View
ICS810251AGI REVISION B OCTOBER 5, 2012
1
©2012 Integrated Device Technology, Inc.
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Integrated Device Technology Electronic Components Datasheet

ICS810251I Datasheet

VCXO and Synchronous Ethernet Jitter Attenuator

No Preview Available !

ICS810251I pdf
ICS810251I Data Sheet
VCXO AND SYNCHRONOUS ETHERNET JITTER ATTENUATOR
Table 1. Pin Descriptions
Number
1
2, 9, 12
3
4
5V
6
7V
8, 15
10,
11
13, 14
16
Name
PLL_SEL
GND
Reserved
Q
DDO
OE
DDA
VDD
XTAL_OUT,
XTAL_IN
LF0, LF1
CLK_IN
Type
Input
Pullup
Power
Reserved
Output
Power
Input
Power
Power
Pullup
Input
Analog
Input/
Output
Input
Pulldown
Description
When logic HIGH, the VCXO-PLL is enabled. When LOW, the VCXO-PLL is in
bypass mode. LVCMOS/LVTTL interface levels.
Power supply ground.
Reserved pin. Do not connect.
Single-ended clock output. LVCMOS/ LVTTL interface levels.
Output power supply pin.
Output enable pin for Q output. LVCMOS/LVTTL interface levels.
Analog supply pin.
Core supply pins.
VCXO crystal oscillator interface. XTAL_IN is the input. XTAL_OUT is the output.
Loop filter connection node pins.
Single-ended clock input. LVCMOS/LVTTL interface levels.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
Symbol
CIN
Parameter
Input Capacitance
CPD Power Dissipation Capacitance
RPULLUP
Input Pullup Resistor
RPULLDOWN Input Pulldown Resistor
ROUT
Output Impedance
Test Conditions
VDD, VDDO = 3.465V
VDD, VDDO = 2.625V
VDDO = 3.3V±5%
VDDO = 2.5V±5%
Minimum
Typical
4p
8
5
51
51
15
20
Maximum
Units
F
pF
pF
k
k
ICS810251AGI REVISION B OCTOBER 5, 2012
2
©2012 Integrated Device Technology, Inc.


Part Number ICS810251I
Description VCXO and Synchronous Ethernet Jitter Attenuator
Maker Integrated Device Technology
Total Page 15 Pages
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