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ICS1894-40 Datasheet

10BASE-T/100BASE-TX INTEGRATED PHYCEIVER

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ICS1894-40 pdf
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DATASHEET
10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE
ICS1894-40
Description
The ICS1894-40 is a low-power, physical-layer device
(PHY) that supports the ISO/IEC 10Base-T and
100Base-TX Carrier-Sense Multiple Access/Collision
Detection (CSMA/CD) Ethernet standards, ISO/IEC
8802.3. It is intended for RMII/MII, Node/Repeater
applications and includes the Auto-MDIX feature that
automatically corrects crossover errors in plant wiring.
The ICS1894-40 incorporates Digital-Signal Processing
(DSP) control in its Physical-Medium Dependent (PMD)
sub-layer. As a result, it can transmit and receive data on
unshielded twisted-pair (UTP) category 5 cables with
attenuation in excess of 24 dB at 100MHz.
The ICS1894-40 provides a Serial-Management Interface
for exchanging command and status information with a
Station-Management (STA) entity. The ICS1894-40
Media-Dependent Interface (MDI) can be configured to
provide either half-duplex or full-duplex operation at data
rates of 10 Mb/s or 100Mb/s.
In addition, the ICS1894-40 includes a programmable LED
and interrupt output function. The LED outputs can be
configured through registers to indicate the occurance of
certain events such as LINK, COLLISION, ACTIVITY, etc.
The purpose of the programmable interrupt output is to
notify the PHY controller device immediately when a certain
event happens instead of having the PHY controller
continuously poll the PHY. The events that could be used to
generate interrupts are: receiver error, Jabber, page
received, parallel detect fault, link partner acknowledge, link
status change, auto-negotiation complete, remote fault,
collision, etc.
The ICS1894-40 has deep power modes that can result in
significant power savings when the link is broken.
Applications: NIC cards, PC motherboards, switches,
routers, DSL and cable modems, game machines, printers,
network connected appliances, and industrial equipment.
Features
Supports category 5 cables and above with attenuation in
excess of 24dB at 100 MHz.
Single-chip, fully integrated PHY provides PCS, PMA,
PMD, and AUTONEG sub layers functions of IEEE
standard.
10Base-T and 100Base-TX IEEE 8802.3 compliant
MIIM (MDC/MDIO) management bus for PHY register
configuration
RMII interface support with external 50 MHz system clock
Single 3.3V power supply
Highly configurable, supports:
– Media Independent Interface (MII)
– Auto-Negotiation with Parallel detection
– Node applications, managed or unmanaged
– 10M or 100M full and half-duplex modes
– Loopback mode for Diagnostic Functions
Auto-MDI/MDIX crossover correction
Low-power CMOS (typically 300 mW)
Power-Down mode (typically 21mW)
Clock and crystal supported in MII mode
Programmable LEDs
Interrupt output pin
Fully integrated, DSP-based PMD includes:
– Adaptive equalization and baseline-wander
correction
– Transmit wave shaping and stream cipher
scrambler
– MLT-3 encoder and NRZ/NRZI encoder
Core power supply (3.3 V)
3.3 V/1.8 V VDDIO operation supported
Smart power control with deep power down feature
Available in 40-pin (6mm x 6mm) QFN package, Pb-free
Industrial Temp and Lead Free
IDT® 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE
1
ICS1894-40 REV G 060110


Integrated Device Technology Electronic Components Datasheet

ICS1894-40 Datasheet

10BASE-T/100BASE-TX INTEGRATED PHYCEIVER

No Preview Available !

ICS1894-40 pdf
ICS1894-40
10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE
Block Diagram
www.DataSPhHeeYt4CUE.coIVmER
10/100 MII/RMII
MAC
Interface
Interface
MUX
MII
Management
Interface
MII
Extended
Register
Set
PCS
• Framer
• CRS/COL
Detection
• Parallel to Serial
• 4B/5B
Low-Jitter
Clock
Synthesizer
Clock
100Base-T
PMA
• Clock Recovery
• Link Monitor
• Signal Detection
• Error Detection
10Base-T
Smart Power
Control
Block
Power
TP_PMD
• MLT-3
• Stream Cipher
• Adaptive Equalizer
• Baseline Wander
Correction
Configuration
and Status
Integrated
Switch
Auto-
Negotiation
Twisted-
Pair
Interface to
Magnetics
Modules and
RJ45
Connector
LEDs and PHY
Address
Pin Assignment
AMAMDIDXIX
TPT_PA_PAP
TP_AN
TP_AN
VSS
VSS
VDD
VDD
TP_BN
TPT_PB_NBP
TP_VBDPD
VTDCDSR
TCSVRSS
VSS
1 1 3131
NLG40 Without Ground Connecting to
NLG40 WithouTthGerromuanldPCaodnnecting to
Thermal Pad
11
11
21
21
TXTXDD0 0
TXTXEENN
SPEED/TXCLK
SPEED/TXCLK
NOD/RXER
NOD/RXER
ANSEL/RXCLK
ATNXSEERL/RXCLK
TXSEPREED
SRPEMEIID/RXDV
RFMDIIP/RXX/RDXVD0
FDSIP/LXE/RDX4D0
SI/LED4
40-pin MLF
40-pin MLF
IDT® 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE
2
ICS1894-40 REV G 060110


Part Number ICS1894-40
Description 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER
Maker Integrated Device Technology
Total Page 30 Pages
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