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Infineon Technologies Electronic Components Datasheet

HYB39S256160DCL Datasheet

(HYB39S256xxxD) 256 MBit Synchronous DRAM

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HYB39S256160DCL pdf
HYB39S256400/800/160DT(L)/DC(L)
256MBit Synchronous DRAM
256 MBit Synchronous DRAM
High Performance:
-6 -7 -7.5 -8 Units
fCK 166 143 133 125 MHz
tCK3 6
7 7.5 8
ns
tAC3 5
5.4 5.4
6
ns
tCK2 7.5 7.5 10 10
ns
tAC2 5.4 5.4
6
6
ns
Fully Synchronous to Positive Clock Edge
0 to 70 °C operating temperature
Four Banks controlled by BA0 & BA1
Programmable CAS Latency: 2 & 3
www.DataSheet4U.coPmrogrammable Wrap Sequence: Sequential
or Interleave
Programmable Burst Length:
1, 2, 4, 8 and full page
Multiple Burst Read with Single Write
Operation
Automatic and Controlled Precharge
Command
Data Mask for Read / Write control (x4, x8)
Data Mask for byte control (x16)
Auto Refresh (CBR) and Self Refresh
Power Down and Clock Suspend Mode
8192 refresh cycles / 64 ms (7,8 µs)
Random Column Address every CLK
( 1-N Rule)
Single 3.3V +/- 0.3V Power Supply
LVTTL Interface versions
Plastic Packages:
P-TSOPII-54 400mil width (x4, x8, x16)
Chipsize Packages:
54 ball TFBGA (12 mm x 8 mm)
-6 parts for PC166 3-3-3 operation
-7 parts for PC133 2-2-2 operation
-7.5 parts for PC133 3-3-3 operation
-8 parts for PC100 2-2-2 operation
The HYB39S256400/800/160DT(L) are four bank Synchronous DRAM’s organized as 4 banks x
16MBit x4, 4 banks x 8MBit x8 and 4 banks x 4Mbit x16 respectively. These synchronous devices
achieve high speed data transfer rates for CAS-latencies by employing a chip architecture that
prefetches multiple bits and then synchronizes the output data to a system clock. The chip is
fabricated with INFINEON’s advanced 0.14 µm 256MBit DRAM process technology.
The device is designed to comply with all industry standards set for synchronous DRAM products,
both electrically and mechanically. All of the control, address, data input and output circuits are
synchronized with the positive edge of an externally supplied clock.
Operating the four memory banks in an interleave fashion allows random access operation to occur
at a higher rate than is possible with standard DRAMs. A sequential and gapless data rate is
possible depending on burst length, CAS latency and speed grade of the device.
Auto Refresh (CBR) and Self Refresh operation are supported. These devices operate with a single
3.3V +/- 0.3V power supply. All 256Mbit components are available in TSOPII-54 and TFBGA-54
packages.
INFINEON Technologies
1
2002-04-23


Infineon Technologies Electronic Components Datasheet

HYB39S256160DCL Datasheet

(HYB39S256xxxD) 256 MBit Synchronous DRAM

No Preview Available !

HYB39S256160DCL pdf
HYB39S256400/800/160DT(L)/DC(L)
256MBit Synchronous DRAM
Ordering Information
Type
Speed Grade
Package
Description
HYB 39S256400DT-6
HYB 39S256400DT-7
HYB 39S256400DT-7.5
HYB 39S256400DT-8
HYB 39S256800DT-6
HYB 39S256800DT-7
HYB 39S256800DT-7.5
HYB 39S256800DT-8
HYB 39S256160DT-6
HYB 39S256160DT-7
HYB 39S256160DT-7.5
HYB 39S256160DT-8
HYB39S256800DTL-x
PC166-333-520
PC133-222-520
PC133-333-520
PC100-222-620
PC166-333-520
PC133-222-520
PC133-333-520
PC100-222-620
PC166-333-520
PC133-222-520
PC133-333-520
PC100-222-620
HYB39S256160DTL-x
www.DataSheet4U.com
HYB39S256xx0DC(L)-x
P-TSOP-54-2 (400mil)
P-TSOP-54-2 (400mil)
P-TSOP-54-2 (400mil)
P-TSOP-54-2 (400mil)
P-TSOP-54-2 (400mil)
P-TSOP-54-2 (400mil)
P-TSOP-54-2 (400mil)
P-TSOP-54-2 (400mil)
P-TSOP-54-2 (400mil)
P-TSOP-54-2 (400mil)
P-TSOP-54-2 (400mil)
P-TSOP-54-2 (400mil)
P-TSOP-54-2 (400mil)
P-TSOP-54-2 (400mil)
P-TFBGA-54
166MHz 4B x 16M x 4 SDRAM
143MHz 4B x 16M x 4 SDRAM
133MHz 4B x 16M x 4 SDRAM
125MHz 4B x 16M x 4 SDRAM
166MHz 4B x 8M x 8 SDRAM
143MHz 4B x 8M x 8 SDRAM
133MHz 4B x 8M x 8 SDRAM
125MHz 4B x 8M x 8 SDRAM
166MHz 4B x 4M x 16 SDRAM
143MHz 4B x 4M x 16 SDRAM
133MHz 4B x 4M x 16 SDRAM
125MHz 4B x 4M x 16 SDRAM
4B x 8M x 8 SDRAM Low Power
Versions (on request)
4B x 4M x 16 SDRAM Low Power
Versions (on request)
(on request)
Pin Description:
CLK
CKE
CS
RAS
CAS
WE
A0-A12
BA0, BA1
Clock Input
Clock Enable
Chip Select
Row Address Strobe
Column Address Strobe
Write Enable
Address Inputs
Bank Select
DQx
DQM, LDQM, UDQM
Data Input /Output
Data Mask
VDD
VSS
VDDQ
VSSQ
NC
Power (+3.3V)
Ground
Power for DQ’s (+ 3.3V)
Ground for DQ’s
not connected
INFINEON Technologies
2
2002-04-23


Part Number HYB39S256160DCL
Description (HYB39S256xxxD) 256 MBit Synchronous DRAM
Maker Infineon Technologies
Total Page 22 Pages
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