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Integrated Silicon Solution Electronic Components Datasheet

IS61QDPB41M18A2 Datasheet

18Mb QUADP (Burst 4) SYNCHRONOUS SRAM

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IS61QDPB41M18A2 pdf
IS61QDPB41M18A/A1/A2
IS61QDPB451236A/A1/A2
1Mx18, 512Kx36
18Mb QUADP (Burst 4) SYNCHRONOUS SRAM
(2.5 Cycle Read Latency)
NOVEMBER 2014
FEATURES
DESCRIPTION
512Kx36 and 1Mx18 configuration available.
On-chip Delay-Locked Loop (DLL) for wide data
valid window.
Separate independent read and write ports with
concurrent read and write operations.
Synchronous pipeline read with late write operation.
Double Data Rate (DDR) interface for read and
write input ports.
2.5 cycle read latency.
Fixed 4-bit burst for read and write operations.
Clock stop support.
The 18Mb IS61QDPB451236A/A1/A2 and
IS61QDPB41M18A/A1/A2 are synchronous, high-
performance CMOS static random access memory (SRAM)
devices. These SRAMs have separate I/Os, eliminating the
need for high-speed bus turnaround. The rising edge of K
clock initiates the read/write operation, and all internal
operations are self-timed. Refer to the Timing Reference
Diagram for Truth Table for a description of the basic
operations of these QUADP (Burst of 4) SRAMs. Read and
write addresses are registered on alternating rising edges of
the K clock. Reads and writes are performed in double data
rate.
Two input clocks (K and K#) for address and control
registering at rising edges only.
Two echo clocks (CQ and CQ#) that are delivered
simultaneously with data.
The following are registered internally on the rising edge of
the K clock:
Read/write address
Read enable
Data Valid Pin (QVLD).
Write enable
+1.8V core power supply and 1.5, 1.8V VDDQ, used
with 0.75, 0.9V VREF.
HSTL input and output interface.
Registered addresses, write and read controls, byte
writes, data in, and data outputs.
Byte writes for burst addresses 1 and 3
Data-in for burst addresses 1 and 3
The following are registered on the rising edge of the K#
clock:
Byte writes for burst addresses 2 and 4
Full data coherency.
Data-in for burst addresses 2 and 4
Boundary scan using limited set of JTAG 1149.1
functions.
Byte write capability.
Fine ball grid array (FBGA) package:
13mmx15mm and 15mmx17mm body size
165-ball (11 x 15) array
Programmable impedance output drivers via 5x
user-supplied precision resistor.
Byte writes can change with the corresponding data-in to
enable or disable writes on a per-byte basis. An internal write
buffer enables the data-ins to be registered one cycle after
the write address. The first data-in burst is clocked one cycle
later than the write command signal, and the second burst is
timed to the following rising edge of the K# clock. Two full
clock cycles are required to complete a write operation.
ODT (On Die Termination) feature is supported
optionally on data input, K/K#, and BWx#.
The end of top mark (A/A1/A2) is to define options.
IS61QDPB451236A : Don’t care ODT function
and pin connection
IS61QDPB451236A 1 : Option1
IS61QDPB451236A 2 : Option2
During the burst read operation, the data-outs from the first
and third bursts are updated from output registers of the third
and fourth rising edges of the K# clock (starting 2.5 cycles
later after read command). The data-outs from the second
and fourth bursts are updated with the fourth and fifth rising
edges of the K clock where the read command receives at
the first rising edge of K. Two full clock cycles are required to
complete a read operation.
Refer to more detail description at page 6 for each
ODT option.
The device is operated with a single +1.8V power supply
and is compatible with HSTL I/O interfaces.
Copyright © 2014 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to
obtain the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can
reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such
applications unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that:
a.) the risk of injury or damage has been minimized;
b.) the user assume all such risks; and
c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances
Integrated Silicon Solution, Inc.- www.issi.com
Rev. B
10/02/2014
1


Integrated Silicon Solution Electronic Components Datasheet

IS61QDPB41M18A2 Datasheet

18Mb QUADP (Burst 4) SYNCHRONOUS SRAM

No Preview Available !

IS61QDPB41M18A2 pdf
IS61QDPB41M18A/A1/A2
IS61QDPB451236A/A1/A2
Package ballout and description
x36 FBGA Ball ballout (Top View)
1234
A CQ# NC/SA1 NC/SA1 W#
B Q27 Q18 D18
SA
C D27 Q28 D19 VSS
D D28 D20 Q19 VSS
E
Q29
D29
Q20
VDDQ
F
Q30
Q21
D21
VDDQ
G
D30
D22
Q22
VDDQ
H Doff#
VREF
VDDQ
VDDQ
J
D31
Q31
D23
VDDQ
K
Q32
D32
Q23
VDDQ
L
Q33
Q24
D24
VDDQ
M D33 Q34 D25 VSS
N D34 D26 Q25 VSS
P Q35 D35 Q26
SA
R TDO TCK
SA
SA
5
BW2#
BW3#
SA
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VSS
VSS
SA
SA
SA
6
K#
K
NC
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
SA
QVLD
ODT
7
BW1#
BW0#
SA
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VSS
VSS
SA
SA
SA
8
R#
SA
VSS
VSS
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSS
VSS
SA
SA
9
NC/SA1
D17
D16
Q16
Q15
D14
Q13
VDDQ
D12
Q12
D11
D10
Q10
Q9
SA
10
NC/SA1
Q17
Q7
D15
D6
Q14
D13
VREF
Q4
D3
Q11
Q1
D9
D0
TMS
11
CQ
Q8
D8
D7
Q6
Q5
D5
ZQ
D4
Q3
Q2
D2
D1
Q0
TDI
The following balls are reserved for higher densities: 9A for 36Mb, 3A for 72Mb, 10A for 144Mb, and 2A for 288Mb.
x18 FBGA Ball ballout (Top View)
12 3 456 7 8
A CQ# NC/SA1 NC/SA1 W# BW1# K# NC/SA1 R#
9 10
SA NC/SA1
B NC
Q9
D9 SA NC
K
BW0#
SA
NC
NC
C NC NC D10 VSS SA NC SA VSS NC Q7
D NC D11 Q10 VSS VSS VSS VSS VSS NC NC
E NC
NC
Q11
VDDQ
VSS
VSS
VSS VDDQ NC
D6
F
NC
Q12
D12
VDDQ
VDD
VSS
VDD
VDDQ
NC
NC
G
NC
D13
Q13
VDDQ
VDD
VSS
VDD
VDDQ
NC
NC
H Doff# VREF
VDDQ
VDDQ
VDD
VSS
VDD
VDDQ
VDDQ
VREF
J NC
NC
D14
VDDQ
VDD
VSS
VDD
VDDQ
NC
Q4
K NC
NC
Q14
VDDQ
VDD
VSS
VDD
VDDQ
NC
D3
L
NC
Q15
D15
VDDQ
VSS
VSS
VSS VDDQ NC
NC
M NC NC D16 VSS VSS VSS VSS VSS NC Q1
N NC D17 Q16 VSS SA SA SA VSS NC NC
P NC NC Q17 SA SA QVLD SA SA NC D0
R TDO TCK
SA
SA
SA ODT SA
SA
SA TMS
Notes:
1. The following balls are reserved for higher densities: 3A for 36Mb, 10A for 72Mb, 2A for 144Mb, and 7A for 288Mb.
11
CQ
Q8
D8
D7
Q6
Q5
D5
ZQ
D4
Q3
Q2
D2
D1
Q0
TDI
Integrated Silicon Solution, Inc.- www.issi.com
Rev. B
10/02/2014
2


Part Number IS61QDPB41M18A2
Description 18Mb QUADP (Burst 4) SYNCHRONOUS SRAM
Maker ISSI
Total Page 30 Pages
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