http://www.www.datasheet4u.com

900,000+ Datasheet PDF Search and Download

Datasheet4U offers most rated semiconductors datasheets pdf




Integrated Silicon Solution Electronic Components Datasheet

IS61QDPB24M18A2 Datasheet

72Mb QUADP (Burst 2) Synchronous SRAM

No Preview Available !

IS61QDPB24M18A2 pdf
IS61QDPB24M18A/A1/A2
IS61QDPB22M36A/A1/A2
4Mx18, 2Mx36
72Mb QUADP (Burst 2) Synchronous SRAM
(2.5 CYCLE READ LATENCY)
AUGUST 2014
FEATURES
2Mx36 and 4Mx18 configuration available.
On-chip Delay-Locked Loop (DLL) for wide data
valid window.
Separate independent read and write ports with
concurrent read and write operations.
Synchronous pipeline read with EARLY write
operation.
Double Data Rate (DDR) interface for read and
write input ports.
2.5 Cycle read latency.
Fixed 2-bit burst for read and write operations.
Clock stop support.
Two input clocks (K and K#) for address and control
registering at rising edges only.
Two echo clocks (CQ and CQ#) that are delivered
simultaneously with data.
Data valid pin (QVLD).
+1.8V core power supply and 1.5, 1.8V VDDQ, used
with 0.75, 0.9V VREF.
HSTL input and output interface.
Registered addresses, write and read controls, byte
writes, data in, and data outputs.
Full data coherency.
Boundary scan using limited set of JTAG 1149.1
functions.
Byte Write capability.
Fine ball grid array (FBGA) package option:
13mmx15mm and 15mmx17mm body size
165-ball (11 x 15) array
Programmable impedance output drivers via 5x
user-supplied precision resistor.
ODT (On Die Termination) feature is supported
optionally on data input, K/K#, and BWx#.
The end of top mark (A/A1/A2) is to define options.
IS61QDPB22M36A : Don’t care ODT function
and pin connection
IS61QDPB22M36A1 : Option1
IS61QDPB22M36A2 : Option2
Refer to more detail description at page 6 for each
ODT option.
DESCRIPTION
The and
are synchronous, high-
performance CMOS static random access memory (SRAM)
devices. These SRAMs have separate I/Os, eliminating the
need for high-speed bus turnaround. The rising edge of K
clock initiates the read/write operation, and all internal
operations are self-timed. Refer to the
for a description of the basic
operations of these
SRAMs. Read and
write addresses are registered on alternating rising edges of
the K clock. Read and write performed in double data rate.
The following are registered internally on the rising edge of
the K clock:
Read address
Read enable
Write enable
Data-in for early writes
The following are registered on the rising edge of the K#
clock:
Write address
Byte writes
Data-in for second burst addresses
Byte writes can change with the corresponding data-in to
enable or disable writes on a per-byte basis. An internal write
buffer enables the data-ins to be registered half a cycle
earlier than the write address. The first data-in burst is
clocked at the same time as the write command signal, and
the second burst is timed to the following rising edge of the
K# clock.
During the burst read operation, the data-outs from the first
bursts are updated from output registers of the second rising
edge of the K# clock (starting two and half cycles later after
read command). The data-outs from the second bursts are
updated with the third rising edge of the K clock. The K and
K# clocks are used to time the data-outs.
The device is operated with a single +1.8V power supply and
is compatible with HSTL I/O interface.
Copyright © 2014 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to
obtain the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can
reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such
applications unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that:
a.) the risk of injury or damage has been minimized;
b.) the user assume all such risks; and
c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances
Integrated Silicon Solution, Inc.- www.issi.com
Rev. C
08/21/2014
1


Integrated Silicon Solution Electronic Components Datasheet

IS61QDPB24M18A2 Datasheet

72Mb QUADP (Burst 2) Synchronous SRAM

No Preview Available !

IS61QDPB24M18A2 pdf
IS61QDPB24M18A/A1/A2
IS61QDPB22M36A/A1/A2
Package ballout and description
x36 FBGA Ball Configuration (Top View)
123
A CQ# NC/SA1 SA
45678
W# BW2# K# BW1# R#
B Q27 Q18 D18
SA BW3#
K
BW0#
SA
C D27 Q28 D19 VSS SA SA SA VSS
D D28 D20 Q19 VSS VSS VSS VSS VSS
E Q29 D29 Q20 VDDQ VSS
VSS
VSS
VDDQ
F Q30 Q21 D21 VDDQ VDD
VSS
VDD
VDDQ
G D30 D22 Q22 VDDQ VDD
VSS
VDD
VDDQ
H Doff# VREF
VDDQ
VDDQ
VDD
VSS
VDD
VDDQ
J D31 Q31 D23 VDDQ VDD
VSS
VDD
VDDQ
K Q32 D32 Q23 VDDQ VDD
VSS
VDD
VDDQ
L Q33 Q24 D24 VDDQ VSS
VSS
VSS
VDDQ
M D33 Q34 D25 VSS VSS VSS VSS VSS
N D34 D26 Q25 VSS SA SA SA VSS
P Q35 D35 Q26
SA
SA QVLD SA
SA
R TDO TCK
SA
SA
SA ODT SA
SA
Notes:
The following balls are reserved for higher densities: 10A for 144Mb, and 2A for 288Mb.
9
SA
D17
D16
Q16
Q15
D14
Q13
VDDQ
D12
Q12
D11
D10
Q10
Q9
SA
10
NC/SA1
Q17
Q7
D15
D6
Q14
D13
VREF
Q4
D3
Q11
Q1
D9
D0
TMS
11
CQ
Q8
D8
D7
Q6
Q5
D5
ZQ
D4
Q3
Q2
D2
D1
Q0
TDI
x18 FBGA Ball Configuration (Top View)
123
A CQ# NC/SA1 SA
45678
W# BW1# K# NC/SA1 R#
B NC
Q9
D9 SA NC
K
BW0#
SA
C NC NC D10 VSS SA SA SA VSS
D NC
D11
Q10
VSS
VSS
VSS
VSS
VSS
E NC
NC
Q11
VDDQ
VSS
VSS
VSS
VDDQ
F
NC
Q12
D12
VDDQ
VDD
VSS
VDD
VDDQ
G NC
D13
Q13
VDDQ
VDD
VSS
VDD
VDDQ
H Doff# VREF
VDDQ
VDDQ
VDD
VSS
VDD
VDDQ
J
NC
NC
D14
VDDQ
VDD
VSS
VDD
VDDQ
K NC
NC
Q14
VDDQ
VDD
VSS
VDD
VDDQ
L
NC
Q15
D15
VDDQ
VSS
VSS
VSS
VDDQ
M NC
NC
D16
VSS
VSS
VSS
VSS
VSS
N NC D17 Q16 VSS SA SA SA VSS
P NC
NC Q17 SA
SA QVLD SA
SA
R TDO TCK
SA
SA
SA ODT SA
SA
Notes:
1. The following balls are reserved for higher densities: 2A for 144Mb, and 7A for 288Mb.
9
SA
NC
NC
NC
NC
NC
NC
VDDQ
NC
NC
NC
NC
NC
NC
SA
10
SA
NC
Q7
NC
D6
NC
NC
VREF
Q4
D3
NC
Q1
NC
D0
TMS
11
CQ
Q8
D8
D7
Q6
Q5
D5
ZQ
D4
Q3
Q2
D2
D1
Q0
TDI
Integrated Silicon Solution, Inc.- www.issi.com
Rev. C
08/21/2014
2


Part Number IS61QDPB24M18A2
Description 72Mb QUADP (Burst 2) Synchronous SRAM
Maker ISSI
Total Page 30 Pages
PDF Download
IS61QDPB24M18A2 pdf
Download PDF File
IS61QDPB24M18A2 pdf
View for Mobile






Related Datasheet

1 IS61QDPB24M18A 72Mb QUADP (Burst 2) Synchronous SRAM ISSI
ISSI
IS61QDPB24M18A pdf
2 IS61QDPB24M18A1 72Mb QUADP (Burst 2) Synchronous SRAM ISSI
ISSI
IS61QDPB24M18A1 pdf
3 IS61QDPB24M18A2 72Mb QUADP (Burst 2) Synchronous SRAM ISSI
ISSI
IS61QDPB24M18A2 pdf




Part Number Start With

0    1    2    3    4    5    6    7    8    9    A    B    C    D    E    F    G    H    I    J    K    L    M    N    O    P    Q    R    S    T    U    V    W    X    Y    Z

site map

webmaste! click here

contact us

Buy Components