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Integrated Silicon Solution Electronic Components Datasheet

IS61QDB44M18A Datasheet

72Mb QUAD (Burst 4) SYNCHRONOUS SRAM

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IS61QDB44M18A pdf
IS61QDB44M18A
IS61QDB42M36A
4Mx18, 2Mx36
72Mb QUAD (Burst 4) SYNCHRONOUS SRAM
FEATURES
DESCRIPTION
AUGUST 2014
2Mx36 and 4Mx18 configuration available.
On-chip Delay-Locked Loop (DLL) for wide data
valid window.
Separate independent read and write ports with
concurrent read and write operations.
Synchronous pipeline read with late write operation.
Double Data Rate (DDR) interface for read and
write input ports.
1.5 cycle read latency.
Fixed 4-bit burst for read and write operations.
Clock stop support.
Two input clocks (K and K#) for address and control
registering at rising edges only.
Two output clocks (C and C#) for data output control.
Two echo clocks (CQ and CQ#) that are delivered
simultaneously with data.
+1.8V core power supply and 1.5, 1.8V VDDQ, used
with 0.75, 0.9V VREF.
HSTL input and output interface.
Registered addresses, write and read controls, byte
writes, data in, and data outputs.
Full data coherency.
Boundary scan using limited set of JTAG 1149.1
functions.
Byte write capability.
Fine ball grid array (FBGA) package:
13mmx15mm and 15mmx17mm body size
165-ball (11 x 15) array
Programmable impedance output drivers via 5x
user-supplied precision resistor.
The 72Mb IS61QDB42M36A and IS61QDB44M18A are
synchronous, high-performance CMOS static random access
memory (SRAM) devices. These SRAMs have separate I/Os,
eliminating the need for high-speed bus turnaround. The
rising edge of K clock initiates the read/write operation, and
all internal operations are self-timed. Refer to the Timing
Reference Diagram for Truth Table for a description of the
basic operations of these QUAD (Burst of 4) SRAMs.
Read and write addresses are registered on alternating rising
edges of the K clock. Reads and writes are performed in
double data rate. The following are registered internally on
the rising edge of the K clock:
Read/write address
Read enable
Write enable
Byte writes for burst addresses 1 and 3
Data-in for burst addresses 1 and 3
The following are registered on the rising edge of the K#
clock:
Byte writes for burst addresses 2 and 4
Data-in for burst addresses 2 and 4
Byte writes can change with the corresponding data-in to
enable or disable writes on a per-byte basis. An internal write
buffer enables the data-ins to be registered one cycle after
the write address. The first data-in burst is clocked one cycle
later than the write command signal, and the second burst is
timed to the following rising edge of the K# clock. Two full
clock cycles are required to complete a write operation.
During the burst read operation, the data-outs from the first
and third bursts are updated from output registers of the
second and third rising edges of the C# clock (starting 1.5
cycles later after read command). The data-outs from the
second and fourth bursts are updated with the third and
fourth rising edges of the C clock. The K and K# clocks are
used to time the data-outs whenever the C and C# clocks are
tied high. Two full clock cycles are required to complete a
read operation.
The device is operated with a single +1.8V power supply and
is compatible with HSTL I/O interfaces.
Copyright © 2014 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to
obtain the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can
reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such
applications unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that:
a.) the risk of injury or damage has been minimized;
b.) the user assume all such risks; and
c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances
Integrated Silicon Solution, Inc.- www.issi.com
Rev. B
08/21/2014
1


Integrated Silicon Solution Electronic Components Datasheet

IS61QDB44M18A Datasheet

72Mb QUAD (Burst 4) SYNCHRONOUS SRAM

No Preview Available !

IS61QDB44M18A pdf
IS61QDB44M18A
IS61QDB42M36A
Package ballout and description
x36 FBGA Ball Configuration (Top View)
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
Notes:
1
CQ#
2
NC/SA1
3
SA
45678
W# BW2# K# BW1# R#
Q27 Q18 D18
SA BW3#
K
BW0#
SA
D27 Q28 D19 VSS SA NC SA VSS
D28 D20 Q19 VSS VSS VSS VSS VSS
Q29
D29
Q20
VDDQ
VSS
VSS
VSS
VDDQ
Q30
Q21
D21
VDDQ
VDD
VSS
VDD
VDDQ
D30
D22
Q22
VDDQ
VDD
VSS
VDD
VDDQ
Doff#
VREF
VDDQ
VDDQ
VDD
VSS
VDD
VDDQ
D31
Q31
D23
VDDQ
VDD
VSS
VDD
VDDQ
Q32
D32
Q23
VDDQ
VDD
VSS
VDD
VDDQ
Q33
Q24
D24
VDDQ
VSS
VSS
VSS
VDDQ
D33 Q34 D25 VSS VSS VSS VSS VSS
D34 D26 Q25 VSS SA SA SA VSS
Q35 D35 Q26
SA
SA
C
SA SA
TDO TCK
SA
SA
SA
C#
SA
SA
The following balls are reserved for higher densities: 10A for 144Mb, and 2A for 288Mb.
x18 FBGA Ball Configuration (Top View)
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
Notes:
1.
1
CQ#
NC
NC
NC
NC
NC
NC
Doff#
NC
NC
NC
NC
NC
NC
TDO
2
NC/SA1
Q9
NC
D11
NC
Q12
D13
VREF
NC
NC
Q15
NC
D17
NC
TCK
3
SA
D9
D10
Q10
Q11
D12
Q13
VDDQ
D14
Q14
D15
D16
Q16
Q17
SA
4
W#
SA
VSS
VSS
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSS
VSS
SA
SA
5
BW1#
NC
SA
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VSS
VSS
SA
SA
SA
678
K# NC/SA1 R#
K
BW0#
SA
NC SA VSS
VSS
VSS
VSS
VSS
VSS
VDDQ
VSS
VDD
VDDQ
VSS
VDD
VDDQ
VSS
VSS
VDD
VDD
VDDQ
VDDQ
VSS
VDD
VDDQ
VSS
VSS
VDDQ
VSS
VSS
VSS
SA SA VSS
C SA SA
C# SA SA
The following balls are reserved for higher densities: 2A for 144Mb, and 7A for 288Mb.
9
SA
D17
D16
Q16
Q15
D14
Q13
VDDQ
D12
Q12
D11
D10
Q10
Q9
SA
10
NC/SA1
Q17
Q7
D15
D6
Q14
D13
VREF
Q4
D3
Q11
Q1
D9
D0
TMS
11
CQ
Q8
D8
D7
Q6
Q5
D5
ZQ
D4
Q3
Q2
D2
D1
Q0
TDI
9
SA
NC
NC
NC
NC
NC
NC
VDDQ
NC
NC
NC
NC
NC
NC
SA
10
SA
NC
Q7
NC
D6
NC
NC
VREF
Q4
D3
NC
Q1
NC
D0
TMS
11
CQ
Q8
D8
D7
Q6
Q5
D5
ZQ
D4
Q3
Q2
D2
D1
Q0
TDI
Integrated Silicon Solution, Inc.- www.issi.com
Rev. B
08/21/2014
2


Part Number IS61QDB44M18A
Description 72Mb QUAD (Burst 4) SYNCHRONOUS SRAM
Maker ISSI
Total Page 30 Pages
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