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Integrated Silicon Solution Electronic Components Datasheet

IS61QDB42M36 Datasheet

QUAD (Burst of 4) Synchronous SRAMs

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IS61QDB42M36 pdf
72 Mb (2M x 36 & 4M x 18)
Q7 UAD (Burst o. f 4) Synchronous SRAMs
Q
November 2009
Features
2M x 36 or 4M x 18.
• On-chip delay-locked loop (DLL) for wide data
valid window.
• Separate read and write ports with concurrent
read and write operations.
• Synchronous pipeline read with late write opera-
tion.
• Double data rate (DDR) interface for read and
write input ports.
• Fixed 4-bit burst for read and write operations.
• Clock stop support.
• Two input clocks (K and K) for address and con-
trol registering at rising edges only.
• Two input clocks (C and C) for data output con-
trol.
Industrial temperature available
• Two echo clocks (CQ and CQ) that are delivered
simultaneously with data.
• +1.8V core power supply and 1.5, 1.8V VDDQ,
used with 0.75, 0.9V VREF.
• HSTL input and output levels.
• Registered addresses, write and read controls,
byte writes, data in, and data outputs.
• Full data coherency.
• Boundary scan using limited set of JTAG 1149.1
functions.
• Byte write capability.
• Fine ball grid array (FBGA) package
- 15mm x 17mm body size
- 1mm pitch
- 165-ball (11 x 15) array
• Programmable impedance output drivers via 5x
user-supplied precision resistor.
Description
The 72Mb IS61QDB42M36 and
IS61QDB44M18 are synchronous, high-perfor-
mance CMOS static random access memory
(SRAM) devices. These SRAMs have separate I/Os,
eliminating the need for high-speed bus turnaround.
The rising edge of K clock initiates the read/write
operation, and all internal operations are self-timed.
Refer to the Timing Reference Diagram for Truth
Table on page 8 for a description of the basic opera-
tions of these QUAD (Burst of 4) SRAMs.
Read and write addresses are registered on alter-
nating rising edges of the K clock. Reads and writes
are performed in double data rate. The following are
registered internally on the rising edge of the K
clock:
• Read/write address
• Read enable
• Write enable
• Byte writes for burst addresses 1 and 3
• Data-in for burst addresses 1 and 3
The following are registered on the rising edge of
the K clock:
Integrated Silicon Solution, Inc.
Rev. B
11/10/09
• Byte writes for burst addresses 2 and 4
• Data-in for burst addresses 2 and 4
Byte writes can change with the corresponding data-
in to enable or disable writes on a per-byte basis. An
internal write buffer enables the data-ins to be regis-
tered one cycle after the write address. The first
data-in burst is clocked one cycle later than the write
command signal, and the second burst is timed to
the following rising edge of the K clock. Two full
clock cycles are required to complete a write opera-
tion.
During the burst read operation, the data-outs from
the first and third bursts are updated from output
registers off the second and fourth rising edges of
the C clock (starting 1.5 cycles later). The data-outs
from the second and fourth bursts are updated with
the third and fifth rising edges of the C clock. The K
and K clocks are used to time the data-outs when-
ever the C and C clocks are tied high. Two full clock
cycles are required to complete a read operation
The device is operated with a single +1.8V power
supply and is compatible with HSTL I/O interfaces.
1


Integrated Silicon Solution Electronic Components Datasheet

IS61QDB42M36 Datasheet

QUAD (Burst of 4) Synchronous SRAMs

No Preview Available !

IS61QDB42M36 pdf
7Q23QUMADb
(2M x 36 & 4M x 18)
(Burst of 4) Synchronous
SRAMs
I®
x36 FBGA Pinout (Top View)
123456789
A CQ NC/SA* SA
W BW2
K
BW1
R
SA
B Q27 Q18 D18 SA BW3 K BW0 SA D17
C D27 Q28 D19 VSS SA NC SA VSS D16
D D28 D20 Q19 VSS VSS VSS VSS VSS Q16
E Q29
D29
Q20
VDDQ
VSS
VSS
VSS
VDDQ
Q15
F Q30
Q21
D21
VDDQ
VDD
VSS
VDD
VDDQ
D14
G D30
D22
Q22
VDDQ
VDD
VSS
VDD
VDDQ
Q13
H
Doff
VREF
VDDQ
VDDQ
VDD
VSS
VDD
VDDQ
VDDQ
J D31
Q31
D23
VDDQ
VDD
VSS
VDD
VDDQ
D12
K Q32
D32
Q23
VDDQ
VDD
VSS
VDD
VDDQ
Q12
L Q33
Q24
D24
VDDQ
VSS
VSS
VSS
VDDQ
D11
M D33 Q34 D25 VSS VSS VSS VSS VSS D10
N D34 D26 Q25 VSS
SA
SA
SA VSS Q10
P Q35 D35 Q26
SA
SA
C
SA SA Q9
R TDO
TCK
SA
SA
SA
C
SA SA SA
Note: *The following pins are reserved for higher densities: 10A for 144Mb, and 2A for 288Mb.
x18 FBGA Pinout (Top View)
1234567
A CQ NC/SA* SA
W BW1 K
NC
B NC Q9 D9 SA NC
K BW0
C NC NC D10 VSS SA NC SA
D NC D11 Q10 VSS VSS VSS VSS
E NC
NC
Q11
VDDQ
VSS
VSS
VSS
F NC
Q12
D12
VDDQ
VDD
VSS
VDD
G NC
D13
Q13
VDDQ
VDD
VSS
VDD
H
Doff
VREF
VDDQ
VDDQ
VDD
VSS
VDD
J NC
NC
D14
VDDQ
VDD
VSS
VDD
K NC
NC
Q14
VDDQ
VDD
VSS
VDD
L NC
Q15
D15
VDDQ
VSS
VSS
VSS
M NC NC D16 VSS VSS VSS VSS
N NC
D17 Q16 VSS
SA
SA
SA
P NC
NC Q17 SA
SA
C
SA
R TDO
TCK
SA
SA
SA
C
SA
Note: *The following pins are reserved for higher densities: 2A for 144Mb.
8
R
SA
VSS
VSS
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSS
VSS
SA
SA
9
SA
NC
NC
NC
NC
NC
NC
VDDQ
NC
NC
NC
NC
NC
NC
SA
10
NC/SA*
Q17
Q7
D15
D6
Q14
D13
VREF
Q4
D3
Q11
Q1
D9
D0
TMS
10
SA
NC
Q7
NC
D6
NC
NC
VREF
Q4
D3
NC
Q1
NC
D0
TMS
11
CQ
Q8
D8
D7
Q6
Q5
D5
ZQ
D4
Q3
Q2
D2
D1
Q0
TDI
11
CQ
Q8
D8
D7
Q6
Q5
D5
ZQ
D4
Q3
Q2
D2
D1
Q0
TDI
2 Integrated Silicon Solution, Inc.
Rev.
11/10/09


Part Number IS61QDB42M36
Description QUAD (Burst of 4) Synchronous SRAMs
Maker ISSI
Total Page 28 Pages
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