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EI68C681 Datasheet Preview

EI68C681 Datasheet

DUAL UART

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EI68C681 pdf
Semiconductor, Inc.
Ei68C681
Ei88C681
DUAL UART
FEATURES
• Full duplex, dual channel asynchronous
receiver and transmitter
• Quadruple-buffered receiver and transmitter
• Stop bits programmable in 1/16-bit increments
• Internal bit rate generator with 23 bit rates
• Independent bit rate selection for each Rx
and Tx
• Maximum bit rate: 1 x clock - 2 Mb/sec., 16
x clock- 250 Kb/sec.
• Normal, auto-echo, local loop-back and
remote loop-back modes
• Multi-function 16-bit counter/timer
• Interrupt output with 8 maskable interrupt
ing conditions
• Interrupt vector output on acknowledge
• Programmable interrupt daisy chain
• Up to 15 I/O pins (depending on package
and version)
• Multidrop mode compatible with 8051 nine-
bit mode
• On-chip oscillator for crystal
• Stand-by mode to reduce operating power
• Advanced CMOS low power technology
DESCRIPTION
The Epic Ei88C681/Ei68C681 DUART Dual Universal
Asynchronous Receiver and Transmitter is a data com-
munication device that provides two fully independent full
duplex asynchronous communication channels in a
single package. The DUART is designed for use in
microprocessor based systems and may be used in a
polled or interrupt driven environment.
Two basic versions of the DUART are available, each
optimized for use with various microprocessor families:
the 88C81 for 8085/85, 8080/88, Z80, Z8000, 68XX and
65XX family based systems., and the 68C681 for 68000
family based systems. A programmable mode of the
Ei88C681 versions provides an interrupt daisy chain for
use in Z80 and Z8000 based systems. The bus inter-
faces are however general enough to allow interfacing
with other microprocessors and microcontrollers. The
88C681 and 68C681 are enhanced versions of the
Signetics 2681 and the Motorola 68681, and are pin and
function compatible with those devices. Each channel of
the DUART may be independently programmed for
operating mode and data format. The operating speed of
each receiver and transmitter can beselected from baud
rate generator, from the multi-purpose on chip
counter/timer or from an external 1 x or 16 x clock.The bit
rate generator can operate directly from a crystal connect-
ed across two pins or from an external clock. The ability to
independently program the operating speed of the receiv-
er and transmitter of each channel makes the DUART
attractive for split-speed channel application such as clus-
tered terminal systems. Both receive and transmit data is
quadruple-buffered in on-chip FIFO to minimize the risk of
receiver overrun or to reduce overhead in interrupt-drive
applications.
PIN CONFIGURATION
Part Numbers May Be Marked With "IMP" or "Ei."
A1 1
40 VCC
IP3 2
39 IP4
A2 3
38 IP5
IP1 4
37 IACK•
A3 5
36 IP2
A4 6
IPO 7
35 CS•
E 34 RESET•
R/W• 8
i 33 X2
DTACK• 9
6 32 X1/CLK
RxDB 10 8 31 RxDA
TxDB 11 C 30 TxDA
OP1 12 6 29 OP0
OP3 13 8 28 OP2
OP5 14 1 27 OP4
OP7 15
26 OP6
D1 16
25 D0
D3 17
24 D2
D5
D7
GND
18
19
20
23 D4
22 D6
21 INTR•
40-PIN DIP
A0 1
40 VCC
IP3 2
39 IP4/IEI
A1 3
38 IP5/IEO
IP1 4
37 IP6/IACKN
A2 5
36 IP2
6 5 4 3 2 1 44 43 42 41 40
A3
IPO
WRN
RDN
6
7
8
9
E
35 CEN
34 RESET
i 33 X2
A4 7
IP0 8
R/WN 9
8 32 X1/CLK DTACK 10
39 CS
38 RESET
37 X2
36 X1/CLK
A3 7
IP0 8
WR• 9
RD• 10
RxDB 10 8 31 RxDA
RXDB 11
35 RXDA
RXDB 11
TxDB 11 C 30 TxDA
NC 12
Ei68C681
34 NC
NC 12
OP1 12 6 29 OP0
TXDB 13
33 TXDA
TXDB 13
OP3 13 8 28 OP2
OP5 14 1 27 OP4
OP7 15
26 OP6
D1 16
25 D0
OP1
OP3
OP5
OP7
14
15
16
17
32 OP0
31 OP2
30 OP4
29 OP6
OP1 14
OP3 15
OP5 16
OP7 17
D3 17
24 D2
18 19 20 21 22 23 24 25 26 27 28
D5 18
23 D4
D7 19
22 D6
GND 20
21 INTRN
Ei88C681
39 CE•
38 RESET
37 X2
36 X1/CLK•
35 RXDA
34 NC
33 TXDA
32 OP0
31 OP2
30 OP4
29 OP6
40-PIN DIP
44-PIN PLCC
44-PIN PLCC
13
For additional information, contact IMP, Inc. at 408.432.9100 or visit www.impweb.com
IMP, Inc. acquired Epic products on January 26, 2001. (see press release at http://www.impweb.com/PRESS/PR012601.htm)



IMP
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EI68C681 Datasheet Preview

EI68C681 Datasheet

DUAL UART

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EI68C681 pdf
Semiconductor, Inc.
The DUART provides a flow control capability to inhibit
transmission from a remote device when the buffer of
the receiving DUART is full, thus preventing loss of
data. The DUART also provides a general purpose 16-
bit counter/timer (which may also be used as a
programmable bit rate generator), a multipurpose input
port and a multipurpose output port.
Ei68C681
Ei88C681
DUAL UART
These ports can be used as general purpose I/O ports
or can be assigned specific functions such as clock
inputs or status/interrupt outputs under program control.
The Ei68C681 are fabricated using Epic’s advanced
CMOS process to provide high performance and low
power consumption.
BLOCK DIAGRAM
D0-D7
8
R/W•
DTACK•
CE•
A0-A3
RESET•
4
INTR•
IACK•
BUS BUFFER
OPERATION
CONTROL
ADDRESS
DECODE
R/W CONTROL
INTERRUPT
CONTROL
IMR
ISR
IVR
X1/CLK
X2
TIMING
AND
CONTROL
LOGIC
14
CHANNEL
TRANSMIT
LOGIC
RECEIVE
LOGIC
TxDA
RxDA
CHANNEL B
(AS ABOVE)
INPUT PORT
IPCR
ACR
TxDB
RxDB
6 IP0-IP6
OUTPUT PORT
OPCR
OPR
8
VCC
GND


Part Number EI68C681
Description DUAL UART
Maker IMP
Total Page 2 Pages
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