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EI16C550 Datasheet Preview

EI16C550 Datasheet

FIFO UART

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EI16C550 pdf
Ei16C550
FIFO UART
Semiconductor, Inc.
FEATURES
ï 5V Operation
ï Tri-StateÆTTL drive capabilities for bi-
directional data bus and control bus
ï Full duplex asynchronous receiver and transmitter ï Line break generation and detection
ï Easily interfaces to most popular micro-
processors
ï Adds or deletes standard asynchronous
communication bits (start, stop, and parity) to or
from a serial data stream
ï Internal diagnostic capabilities:
- Loopback controls for communications link fault
isolation
- Break, parity overrun, and framing error simulation
ï Independently controlled transmitter, receiver,
line status, and data set interrupts
ï Fully prioritized interrupt systems controls
ï 16 byte FIFO for reduced CPU overhead
ï Programmable baud rate generator allows
division of any input clock by 1 to (216-1) and
generates the internal 16 x clock
ï Independent receiver clock input
ï MODEM control functions (CTS, RTS, DSR,
DTR, RI,and DCD)
ï Fully programmable serial interface
characteristics:
- 5, 6, 7, or 8 bit characters
- Even, odd, or no-parity bit generation and
detection
- 1, 1.5, or 2 stop bit generation
- Baud generation (DC to 56k baud)
DESCRIPTION
The Epic Ei16C550 Universal Asynchronous Receiver
Transmitter (UART) is a CMOS-VLSI communication
device in a single package.
The UART performs serial to parallel conversion on
data characters received from a peripheral device or a
MODEM, and parallel-to-serial conversions on data charac-
ters received from the CPU. The CPU can read the complete
status of the UART at any time during the functional operation.
Status information reported includes the type and condition of
the transfer operation being performed by the UART, as well
as any error conditions (party, overrun, framing, or break
detect).
ï False start bit detection
ï Complete status reporting capabilities
Part Numbers May Be Marked With "IMP" or "Ei."
PIN CONFIGURATION
D0 1
40 VCC
D1 2
39 RIï
D2 3
38 DCDï
D3 4
37 DSRï
D4 5
36 CTSï
D5 6
D6 7
D7 8
E
i
35 MR
34 OUT1ï
33 DTRï
RCLK 9
1 32 RTSï
SIN 10 6 31 OUT2ï
SOUT 11 C 30 INTRPT
CS0 12 5 29 RXRDYï
CS1 13 5 28 A0
CS2ï 14 0 27 A1
BAUDOUTï 15
26 A2
XTAL1 16
25 ADSï
XTAL2 17
24 TXRDYï
DOSTRï 18
23 DDIS
VSS 19
22 DISTR
20 21 DISTRï
40-PIN DIP
D5
D6
D7
RCLK
SIN
NC
SOUT
CS0
CS1
CS2ï
BAUD-
OUTï
7
8
9
10
11
12
13
14
15
16
17
Ei16C550
39 MR
38 OUT1ï
37 DTRï
36 RTSï
35 OUT2ï
34 NC
33 INTRPT
32 RXRDYï
31 A0
30 A1
29 A2
N.C. 1
D5 2
D6 3
D7 4
RCLK 5
N.C. 6
RX 7
TX 8
CS0 9
CS1 10
CS2 ï 11
BAUDOUT ï 12
Ei16C550
36 N.C.
35 RESET
34 OP1 ï
33 DTR ï
32 RTS ï
31 OP2 ï
30 INT
29 RXRDY ï
28 A0
27 A1
26 A2
25 N.C.
44-PIN PLCC
48-PIN TQFP
7
For additional information, contact IMP, Inc. at 408.432.9100 or visit www.impweb.com
IMP, Inc. acquired Epic products on January 26, 2001. (see press release at http://www.impweb.com/PRESS/PR012601.htm)



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EI16C550 Datasheet Preview

EI16C550 Datasheet

FIFO UART

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EI16C550 pdf
Ei16C550
FIFO UART
Semiconductor, Inc.
The UART includes a programmable baud generator
which is capable of dividing the timing reference clock
input by divisors of 1 to (216-1), and producing a 16 x
clock to drive the receiver logic. Also included in the
UART is a complete MODEM control capability, and
processor interrupt system that may be software tai-
lored to the users requirement to minimize the com-
puting needed to handle the communications link.
BLOCK DIAGRAM
D7-D0
(1-8)
DATA
BUS
BUFFER
INTERNAL
DATA BUS
A0
A1
A2
CS0
CS1
CS2•
ADR
MR
DISTR
DISTR•
DOSTR
DOSTR•
DDIS
TXRDY•
XTAL1
XTAL2
RXRDY•
(28)
(27)
(26)
(12)
(13)
(14)
(25)
(35) SELECT
(22) AND
(21) CONTROL
(19) LOGIC
(18)
(23)
(24)
(16)
(17)
(29)
POWER (40) 3.3, 5V
SUPPLY (20) GND
RECEIVER
BUFFER
REGISTER
LINE
CONTROL
REGISTER
DIVISOR
LATCH
(LS)
DIVISOR
LATCH
(MS
LINE
STATUS
REGISTER
FIFO
MODEM
CONTROL
REGISTER
MODEM
STATUS
REGISTER
INTERRUPT
ENABLE
REGISTER
INTERRUPT
ID
REGISTER
FIFO
CONTROL
REGISTER
RECEIVER
SHIFT
REGISTER
(10)
SIN
BAUD
GENERATOR
RECEIVER
TIMING
&
CONTROL
(15)
(9) RCLK
BAUDOUT
TRANSMITTER
TIMING
&
CONTROL
INTERRUPT
CONTROL
LOGIC
TRANSMITTER (11)
SHIFT
REGISTER
SOUT
MODEM
CONTROL
LOGIC
(32)
(36)
(33)
(37)
(38)
(39)
(34)
(31)
RTS•
CTS•
DTR•
DSR•
DCD•
RI•
OUT1•
OUT2•
(30) INTRPT
8


Part Number EI16C550
Description FIFO UART
Maker IMP
Total Page 2 Pages
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