http://www.www.datasheet4u.com

900,000+ Datasheet PDF Search and Download

Datasheet4U offers most rated semiconductors datasheets pdf




Integrated Device Technology Electronic Components Datasheet

ICS9LPRS502 Datasheet

56-PIN CK505 W/FULLY INTEGRATED VOLTAGE REGULATOR + INTEGRATED SERIES RESISTOR

No Preview Available !

ICS9LPRS502 pdf
Datasheet
56-PIN CK505 W/FULLY INTEGRATED VOLTAGE
REGULATOR + INTEGRATED SERIES RESISTOR
ICS9LPRS502
Recommended Application:
CK505 compliant clock with fully integrated voltage
regulator and Internal series resistor on differential outputs,
PCIe Gen 1 compliant
Output Features:
• 2 - CPU differential low power push-pull pairs
• 7 - SRC differential low power push-pull pairs
• 1 - CPU/SRC selectable differential low power push-pull
pair
• 1 - SRC/DOT selectable differential low power push-pull
pair
• 5 - PCI, 33MHz
• 1 - PCI_F, 33MHz free running
• 1 - USB, 48MHz
• 1 - REF, 14.318MHz
Key Specifications:
• CPU outputs cycle-cycle jitter < 85ps
• SRC output cycle-cycle jitter < 125ps
• PCI outputs cycle-cycle jitter < 250ps
• +/- 100ppm frequency accuracy on CPU & SRC
clocks
Features/Benefits:
• Does not require external pass transistor for voltage
regulator
• Integrated series resistors on differential outputs,
Zo=50W
• Supports spread spectrum modulation, default is 0.5%
down spread
• Uses external 14.318MHz crystal, external crystal
load caps are required for frequency tuning
• One differential push-pull pair selectable between
SRC and two single-ended outputs
Table 1: CPU Frequency Select Table
Pin Configuration
FSLC2 FSLB1 FSLA1
B0b7 B0b6 B0b5
CPU
MHz
SRC
MHz
PCI REF USB
MHz MHz MHz
0 0 0 266.66
0 0 1 133.33
0 1 0 200.00
0 1 1 166.66 100.00 33.33 14.318 48.00
1 0 0 333.33
1 0 1 100.00
1 1 0 400.00
111
Reserved
1. FSLA and FSLB are low-threshold inputs.Please see VIL_FS and VIH_FS specifications in
the Input/Supply/Common Output Parameters Table for correct values.
Also refer to the Test Clarification Table.
2. FSLC is a three-level input. Please see the VIL_FS and VIH_FS
specifications in the Input/Supply/Common Output Parameters Table for correct values.
DOT
MHz
96.00
PCICLK0/CR#_A 1
VDDPCI 2
PCICLK1/CR#_B 3
PCICLK2/LTE 4
PCICLK3 5
PCICLK4/SRC5_EN 6
PCI_F5/ITP_EN 7
GNDPCI 8
VDD48 9
USB_48MHz/FSLA 10
GND48 11
VDD96I/O 12
DOTT_96/SRCCLKT0 13
DOTC_96/SRCCLKC0 14
GND 15
VDD 16
SRCCLKT1/SE1 17
SRCCLKC1/SE2 18
GND 19
VDDPLL3I/O 20
SRCCLKT2/SATACLKT 21
SRCCLKC2/SATACLKC 22
GNDSRC 23
SRCCLKT3/CR#_C 24
SRCCLKC3/CR#_D 25
VDDSRCI/O 26
SRCCLKT4 27
SRCCLKC4 28
56 SCLK
55 SDATA
54 FSLC/TEST_SEL/REF0
53 VDDREF
52 X1
51 X2
50 GNDREF
49 FSLB/TEST_MODE
48 CK_PWRGD/PD#
47 VDDCPU
46 CPUCLKT0
45 CPUCLKC0
44 GNDCPU
43 CPUCLKT1
42 CPUCLKC1
41 VDDCPUI/O
40 NC
39 CPUCLKT2_ITP/SRCCLKT8
38 CPUCLKC2_ITP/SRCCLKC8
37 VDDSRCI/O
36 SRCCLKT7/CR#_F
35 SRCCLKC7/CR#_E
34 GNDSRC
33 SRCCLKT6
32 SRCCLKC6
31 VDDSRC
30 PCI_STOP#/SRCCLKT5
29 CPU_STOP#/SRCCLKC5
56-SSOP/TSSOP
* Internal Pull-Up Resistor
** Internal Pull-Down Resistor
IDTTM/ICSTM 56-pin CK505 w/Fully Integrated Voltage Regulator + Integrated Series Resistor
1125E—02/26/09
1
Free Datasheet http://www.Datasheet4U.com


Integrated Device Technology Electronic Components Datasheet

ICS9LPRS502 Datasheet

56-PIN CK505 W/FULLY INTEGRATED VOLTAGE REGULATOR + INTEGRATED SERIES RESISTOR

No Preview Available !

ICS9LPRS502 pdf
ICS9LPRS502
56-PIN CK505 W/FULLY INTEGRATED VOLTAGE REGULATOR + INTEGRATED SERIES RESISTOR
Advance Information
SSOP/TSSOP Pin Description
PIN #
PIN NAME
TYPE
1 PCI0/CR#_A
I/O
2 VDDPCI
PWR
3 PCI1/CR#_B
I/O
4 PCI2/TME
5 PCI3
6 PCI4/SRC5_EN
7 PCI_F5/ITP_EN
8 GNDPCI
9 VDD48
10 USB_48MHz/FSLA
11 GND48
12 VDD96_IO
13 DOTT_96/SRCT0
14 DOTC_96/SRCC0
15 GND
16 VDD
I/O
OUT
I/O
I/O
PWR
PWR
I/O
PWR
PWR
OUT
OUT
PWR
PWR
DESCRIPTION
3.3V PCI clock output or Clock Request control A for either SRC0 or SRC2 pair
The power-up default is PCI0 output, but this pin may also be used as a Clock Request control of
SRC pair 0 or SRC pair 2 via SMBus. Before configuring this pin as a Clock Request Pin, the PCI
output must first be disabled in byte 2, bit 0 of SMBus address space . After the PCI output is
disabled (high-Z), the pin can then be set to serve as a Clock Request pin for either SRC pair 2 or
pair 0 using the CR#_A_EN bit located in byte 5 of SMBUs address space.
Byte 5, bit 7
0 = PCI0 enabled (default)
1= CR#_A enabled. Byte 5, bit 6 controls whether CR#_A controls SRC0 or SRC2 pair
Byte 5, bit 6
0 = CR#_A controls SRC0 pair (default),
1= CR#_A controls SRC2 pair
Power supply pin for the PCI outputs, 3.3V nominal
3.3V PCI clock output/Clock Request control B for either SRC1 or SRC4 pair
The power-up default is PCI1 output, but this pin may also be used as a Clock Request control of
SRC pair 1 or SRC pair 4 via SMBus. Before configuring this pin as a Clock Request Pin, the PCI
output must first be disabled in byte 2, bit 1 of SMBus address space . After the PCI output is
disabled (high-Z), the pin can then be set to serve as a Clock Request pin for either SRC pair 1 or
pair 4 using the CR#_B_EN bit located in byte 5 of SMBUs address space.
Byte 5, bit 5
0 = PCI1 enabled (default)
1= CR#_B enabled. Byte 5, bit 6 controls whether CR#_B controls SRC1 or SRC4 pair
Byte 5, bit 4
0 = CR#_B controls SRC1 pair (default)
1= CR#_B controls SRC4 pair
3.3V PCI clock output / Trusted Mode Enable (TME) Latched Input. This pin is sampled on power-
up as follows
0 = Overclocking of CPU and SRC Allowed
1 = Overclocking of CPU and SRC NOT allowed
After being sampled on power-up, this pin becomes a 3.3V PCI Output
3.3V PCI clock output.
3.3V PCI clock output / SRC5 pair or PCI_STOP#/CPU_STOP# enable strap. On powerup, the
logic value on this pin determines if the SRC5 pair is enabled or if CPU_STOP#/PCI_STOP# is
enabled (pins 29 and 30). The latched value controls the pin function on pins 29 and 30 as follows
0 = PCI_STOP#/CPU_STOP#
1 = SRC5/SRC5#
Free running PCI clock output and ITP/SRC8 enable strap. This output is not affected by the state
of the PCI_STOP# pin. On powerup, the state of this pin determines whether pins 38 and 39 are an
ITP or SRC pair.
0 =SRC8/SRC8#
1 = ITP/ITP#
Ground for PCI clocks.
Power supply for USB clock, nominal 3.3V.
Fixed 48MHz USB clock output. 3.3V./ 3.3V tolerant input for CPU frequency selection. Refer to
input electrical characteristics for Vil_FS and Vih_FS values.
Ground pin for the 48MHz outputs.
Power supply for DOT96 output. 1.05 to 3.3V +/-5%.
True clock of SRC or DOT96. The power-up default function is SRC0. After powerup, this pin
function may be changed to DOT96 via SMBus Byte 1, bit 7 as follows:
0= SRC0
1=DOT96
Complement clock of SRC or DOT96. The power-up default function is SRC0#. After powerup, this
pin function may be changed to DOT96# via SMBus Byte 1, bit 7 as follows
0= SRC0#
1=DOT96#
Ground pin for the DOT96 clocks.
Power supply for SRC / SE1 and SE2 clocks, 3.3V nominal.
IDTTM/ICSTM 56-pin CK505 w/Fully Integrated Voltage Regulator + Integrated Series Resistor
2
1125E—02/26/09
Free Datasheet http://www.Datasheet4U.com


Part Number ICS9LPRS502
Description 56-PIN CK505 W/FULLY INTEGRATED VOLTAGE REGULATOR + INTEGRATED SERIES RESISTOR
Maker IDT
Total Page 29 Pages
PDF Download
ICS9LPRS502 pdf
Download PDF File
ICS9LPRS502 pdf
View for Mobile






Related Datasheet

1 ICS9LPRS501 64-PIN CK505 W/FULLY INTEGRATED VOLTAGE REGULATOR + INTEGRATED SERIES RESISTOR IDT
IDT
ICS9LPRS501 pdf
2 ICS9LPRS502 56-PIN CK505 W/FULLY INTEGRATED VOLTAGE REGULATOR + INTEGRATED SERIES RESISTOR IDT
IDT
ICS9LPRS502 pdf




Part Number Start With

0    1    2    3    4    5    6    7    8    9    A    B    C    D    E    F    G    H    I    J    K    L    M    N    O    P    Q    R    S    T    U    V    W    X    Y    Z

site map

webmaste! click here

contact us

Buy Components