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Integrated Device Technology Electronic Components Datasheet

ICS9FG107 Datasheet

Programmable FTG

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ICS9FG107 pdf
DATASHEET
Programmable FTG for Differential P4TM CPU, PCI-Express & SATA
Clocks
ICS9FG107
Description
ICS9FG107 is a Frequency Timing Generator that provides 7
differential output pairs that are compliant to the Intel CK409/CK410
specification. It provides support for PCI-Express, next generation I/
O, and SATA. The part synthesizes several output frequencies from
either a 14.31818 Mhz crystal or a 25 MHz crystal. The device can
also be driven by a reference input clock instead of a crystal. It
provides outputs with cycle-to-cycle jitter of less than 85 ps and
output-to-output skew of less than 85 ps.
ICS9FG107 also provides a copy of the reference clock and 333
MHz PCI output clocks. Frequency selection can be accomplished
via strap pins or SMBus control.
Features/Benefits
• Generates common CPU/PCI Express frequencies from
14.318 MHz or 25 MHz
• Crystal or reference input
• 7 - 0.7V current-mode differential output pairs
• 3 - 33MHz PCI outputs
• 1 - REFOUT
• Supports Serial-ATA at 100 MHz
• Two spread spectrum modes: 0 to -0.5 downspread and
+/-0.25% centerspread
• Unused inputs may be disabled in either driven or Hi-Z
state for power management.
Key Specifications
• Output cycle-to-cycle jitter for DIF outputs < 50 ps (<85ps
@ 266 MHz)
• Output to output skew for DIF outputs < 85 ps
• +/-300 ppm frequency accuracy on output clocks
• 48-pin SSOP/TSSOP package
• Available in RoHS compliant packaging
Funtional Block Diagram
XIN/CLKIN
X2
REFOUT
SCLK
SDATA
DIF_STOP#
SEL14M_25M#
SPREAD
DWNSPRD#
OE (6:0)
FS (2:0)
Control
Logic
Programmable
Spread
PLL1
Programmable
Frequency
Dividers
PCICLK (1:0)
PCICLK_F
DIF (6:0)
DIF# (6:0)
I REF
IDTTM/ICSTM Programmable FTG for Differential P4TM CPU, PCI-Express & SATA Clocks
1
ICS9FG107 REV F 08/21/07


Integrated Device Technology Electronic Components Datasheet

ICS9FG107 Datasheet

Programmable FTG

No Preview Available !

ICS9FG107 pdf
ICS9FG107
Programmable FTG for Differential P4TM CPU, PCI-Express & SATA Clocks
Pin Configuration
XIN/CLKIN 1
X2 2
VDD 3
GND 4
FS2/REFOUT* 5
GND 6
FS0/PCICLK_F* 7
PCICLK0 8
PCICLK1 9
VDD 10
OE_6** 11
DIF_6 12
DIF_6# 13
VDD 14
GND 15
OE_5** 16
DIF_5 17
DIF_5# 18
VDD 19
DIF_4 20
DIF_4# 21
OE_4* 22
SDATA 23
SCLK 24
48 VDDA
47 GNDA
46 IREF
45 DWNSPRD#*
44 FS1**
43 OE_0*
42 DIF_0
41 DIF_0#
40 VDD
39 DIF_1
38 DIF_1#
37 OE_1**
36 VDD
35 GND
34 OE_2**
33 DIF_2
32 DIF_2#
31 VDD
30 DIF_3
29 DIF_3#
28 OE_3*
27 SEL14M_25M#**
26 SPREAD*
25 DIF_STOP#
Notes:
Pins preceeded by * have 120 Kohm pull UP resistors
Pins preceeded by ** have 120 Kohm pull DOWN resistors
FS(2:0) and SEL14M_25M# are latched inputs
Functionality Table
SEL14M_25M#
(FS3)
FS2
FS1 FS0 OUTPUT(MHz)
0
000
100.00
0
001
125.00
0
010
133.33
0
011
166.67
0
100
200.00
0
101
266.66
0
110
333.33
0
111
400.00
1
000
100.00
1
001
125.00
1
010
133.33
1
011
166.67
1
100
200.00
1
101
266.66
1
110
333.33
1
111
400.00
Power Groups
Pin Number
VDD
GND
34
10 6
14,19,31,36,40
15,35
N/A 47
48 47
Description
REFOUT, Digital Inputs, SMBus
PCI Outputs
DIF Outputs
IREF
Analog VDD & GND for PLL Core
IDTTM/ICSTM Programmable FTG for Differential P4TM CPU, PCI-Express & SATA Clocks
2
ICS9FG107 REV F 08/21/07


Part Number ICS9FG107
Description Programmable FTG
Maker IDT
Total Page 18 Pages
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