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Integrated Device Technology Electronic Components Datasheet

ICS932S208 Datasheet

Programmable Timing Control Hub

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ICS932S208 pdf
DATASHEET
PGreongrPa4mTMmaPbrloeceTsimsoinr g Control HubTM for Next
ICS932S208
Recommended Application:
CK409B clock, Intel Yellow Cover part, Server Applications
Output Features:
• 4 - 0.7V current-mode differential CPU pairs
• 1 - 0.7V current-mode differential SRC pair
• 7 - PCI (33MHz)
• 3 - PCICLK_F, (33MHz) free-running
• 1 - USB, 48MHz
• 1 - DOT, 48MHz
• 2 - REF, 14.318MHz
• 4 - 3V66, 66.66MHz
• 1 - VCH/3V66, selectable 48MHz or 66MHz
Key Specifications:
• CPU/SRC outputs cycle-cycle jitter < 125ps
• 3V66 outputs cycle-cycle jitter < 250ps
• PCI outputs cycle-cycle jitter < 250ps
• CPU outputs skew: < 100ps
• +/- 300ppm frequency accuracy on CPU & SRC clocks
Functionality
CPU
B6b5 FS_A FS_B MHz
0 0 100
0 MID Ref/N0
0 0 1 200
1 0 133
1 1 166
1 MID Hi-Z
0 0 200
1
0
1
1 400
0 266
1 1 333
SRC
MHz
100/200
Ref/N1
100/200
100/200
100/200
Hi-Z
100/200
100/200
100/200
100/200
3V66 PCI
MHz MHz
66.66 33.33
Ref/N2 Ref/N3
66.66 33.33
66.66 33.33
66.66 33.33
Hi-Z Hi-Z
66.66 33.33
66.66 33.33
66.66 33.33
66.66 33.33
REF
MHz
14.318
Ref/N4
14.318
14.318
14.318
Hi-Z
14.318
14.318
14.318
14.318
USB/DOT
MHz
48.00
Ref/N5
48.00
48.00
48.00
Hi-Z
48.00
48.00
48.00
48.00
Features/Benefits:
• Supports tight ppm accuracy clocks for Serial-ATA
• Supports spread spectrum modulation, 0 to -0.5%
down spread and +/- 0.25% center spread
• Supports CPU clks up to 400MHz in test mode
• Uses external 14.318MHz crystal
Pin Configuration
REF0 1
REF1 2
VDDREF 3
X1 4
X2 5
GND 6
PCICLK_F0 7
PCICLK_F1 8
PCICLK_F2 9
VDDPCI 10
GND 11
PCICLK0 12
PCICLK1 13
PCICLK2 14
PCICLK3 15
VDDPCI 16
GND 17
PCICLK4 18
PCICLK5 19
PCICLK6 20
PD# 21
3V66_0 22
3V66_1 23
VDD3V66 24
GND 25
3V66_2 26
3V66_3 27
SCLK 28
56 FS_B
55 VDDA
54 GNDA
53 GND
52 IREF
51 FS_A
50 CPUCLKT3
49 CPUCLKC3
48 VDDCPU
47 CPUCLKT2
46 CPUCLKC2
45 GND
44 CPUCLKT1
43 CPUCLKC1
42 VDDCPU
41 CPUCLKT0
40 CPUCLKC0
39 GND
38 SRCCLKT
37 SRCCLKC
36 VDD
35 Vtt_PWRGD#
34 VDD48
33 GND
32 48MHz_DOT
31 48MHz_USB
30 SDATA
29 3V66_4/VCH
56-pin SSOP & TSSOP
IDTTM Programmable Timing Control HubTM for Next Gen P4TM Processor
1
0743G—01/26/10


Integrated Device Technology Electronic Components Datasheet

ICS932S208 Datasheet

Programmable Timing Control Hub

No Preview Available !

ICS932S208 pdf
ICS932S208
Programmable Timing Control HubTM for Next Gen P4TM Processor
Pin Description
PIN #
PIN NAME
1 REF0
2 REF1
3 VDDREF
4 X1
5 X2
6 GND
7 PCICLK_F0
8 PCICLK_F1
9 PCICLK_F2
10 VDDPCI
11 GND
12 PCICLK0
13 PCICLK1
14 PCICLK2
15 PCICLK3
16 VDDPCI
17 GND
18 PCICLK4
19 PCICLK5
20 PCICLK6
21 PD#
22 3V66_0
23 3V66_1
24 VDD3V66
25 GND
26 3V66_2
27 3V66_3
28 SCLK
PIN TYPE
DESCRIPTION
OUT
OUT
PWR
IN
OUT
PWR
OUT
OUT
OUT
PWR
PWR
OUT
OUT
OUT
OUT
PWR
PWR
OUT
OUT
OUT
IN
OUT
OUT
PWR
PWR
OUT
OUT
IN
14.318 MHz reference clock.
14.318 MHz reference clock.
Ref, XTAL power supply, nominal 3.3V
Crystal input, Nominally 14.318MHz.
Crystal output, Nominally 14.318MHz
Ground pin.
Free running PCI clock not affected by PCI_STOP# .
Free running PCI clock not affected by PCI_STOP# .
Free running PCI clock not affected by PCI_STOP# .
Power supply for PCI clocks, nominal 3.3V
Ground pin.
PCI clock output.
PCI clock output.
PCI clock output.
PCI clock output.
Power supply for PCI clocks, nominal 3.3V
Ground pin.
PCI clock output.
PCI clock output.
PCI clock output.
Asynchronous active low input pin used to power down the device into a
low power state. The internal clocks are disabled and the VCO and the
crystal are stopped. The latency of the power down will not be greater
than 1.8ms. Internal pull-up of 150K nominal.
3.3V 66.66MHz clock output
3.3V 66.66MHz clock output
Power pin for the 3V66 clocks.
Ground pin.
3.3V 66.66MHz clock output
3.3V 66.66MHz clock output
Clock pin of I2C circuitry 5V tolerant
IDTTM Programmable Timing Control HubTM for Next Gen P4TM Processor
2
0743G—01/26/10


Part Number ICS932S208
Description Programmable Timing Control Hub
Maker IDT
Total Page 21 Pages
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