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ICS8S89833I Datasheet

1-To-4 Differential-To-LVDS Fanout Buffer w/Internal Termination

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ICS8S89833I pdf
Low Skew, 1-To-4 Differential-To-LVDS
Fanout Buffer w/Internal Termination
ICS8S89833I
DATA SHEET
General Description
The ICS8S89833I is a high speed 1-to-4 Differential-to-LVDS Fanout
Buffer with Internal Termination. The ICS8S89833I is optimized for
high speed and very low output skew, making it suitable for use in
demanding applications such as SONET, 1 Gigabit and 10 Gigabit
Ethernet, and Fibre Channel. The internally terminated differential
input and VREF_AC pin allow other differential signal families such as
LVPECL, LVDS, and CML to be easily interfaced to the input with
minimal use of external components. The device also has an output
enable pin which may be useful for system test and debug purposes.
The ICS8S89833I is packaged in a small 3mm x 3mm 16-pin
VFQFN package which makes it ideal for use in space-constrained
applications.
Features
Four differential LVDS outputs
IN, nIN input pair can accept the following differential input levels:
LVPECL, LVDS, CML
Output frequency: 2GHz
Cycle-to-cycle jitter, RMS: 3.5ps (maximum)
Additive phase jitter, RMS: 0.03ps (typical)
Output skew: 30ps (maximum)
Part-to-part skew: 200ps (maximum)
Propagation Delay: 600ps (maximum)
Full 3.3V supply mode
-40°C to 85°C ambient operating temperature
Available in lead-free (RoHS 6) package
Block Diagram
IN
50
VT
50
nIN
VREF_AC
EN Pullup
DQ
Q0
nQ0
Q1
nQ1
Q2
nQ2
Q3
nQ3
Pin Assignment
16 15 14 13
Q0 1
12 IN
nQ0 2
11 VT
Q1 3
10 VREF_AC
nQ1 4
9 nIN
5 6 78
ICS8S89833I
16-Lead VFQFN
3mm x 3mm x 0.925mm package body
K Package
Top View
ICS8S89833AKI REVISION A JULY 13, 2010
1
©2010 Integrated Device Technology, Inc.


Integrated Device Technology Electronic Components Datasheet

ICS8S89833I Datasheet

1-To-4 Differential-To-LVDS Fanout Buffer w/Internal Termination

No Preview Available !

ICS8S89833I pdf
ICS8S89833I Data Sheet
LOW SKEW, 1-TO-4 DIFFERENTIAL-TO-LVDS FANOUT BUFFER W/INTERNAL TERMINATION
Table 1. Pin Descriptions
Number
1, 2
Name
Q0, nQ0
Type
Output
3, 4 Q1, nQ1 Output
5, 6 Q2, nQ2 Output
Description
Differential output pair. Normally terminated with 100across the pair. LVDS interface
levels.
Differential output pair. Normally terminated with 100across the pair. LVDS interface
levels.
Differential output pair. Normally terminated with 100across the pair. LVDS interface
levels.
7, 14
8
9
10
11
12
13
15, 16
VDD
EN
nIN
VREF_AC
VT
IN
GND
Q3, nQ3
Power
Input
Input
Output
Input
Input
Power
Output
Pullup
Power supply pins.
Synchronizing output enable pin. When LOW, disables outputs. When HIGH, enables
outputs. Internally connected to a 37kpullup resistor. LVTTL / LVCMOS interface levels.
Inverting differential LVPECL clock input. RT = 50termination to VT.
Reference voltage for AC-coupled applications. Equal to VDD - 1.4V (approx.). Maximum
sink/source current is ±2mA.
Input termination center-tap. Each side of the differential input pair terminates to a VT pin.
The VT pins provide a center-tap to a termination network for maximum interface flexibility.
Non-inverting differential clock input. RT = 50termination to VT.
Power supply ground.
Differential output pair. Normally terminated with 100across the pair. LVDS interface
levels.
NOTE: Pullup refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
Symbol
RPULLUP
Parameter
Input Pullup Resistor
Test Conditions
Minimum
Typical
37
Maximum
Units
k
ICS8S89833AKI REVISION A JULY 13, 2010
2
©2010 Integrated Device Technology, Inc.


Part Number ICS8S89833I
Description 1-To-4 Differential-To-LVDS Fanout Buffer w/Internal Termination
Maker IDT
Total Page 16 Pages
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